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authorHaavard Skinnemoen <haavard.skinnemoen@atmel.com>2009-03-23 10:22:41 +0100
committerHaavard Skinnemoen <haavard.skinnemoen@atmel.com>2009-03-23 10:22:41 +0100
commit8206bfae3ab7f99965136384360ba2de0c6f4c3b (patch)
treee11bf0fad2e418e6771e8db7dbcb6630a6053f0c /board/miromico/hammerhead
parentee1702d75a30d076139d1841383a1fa7220a0e11 (diff)
parent58a518c3d8a2c7de11d414e8b903495daee7dc7e (diff)
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Merge branch 'mimc200'
Diffstat (limited to 'board/miromico/hammerhead')
-rw-r--r--board/miromico/hammerhead/hammerhead.c26
1 files changed, 11 insertions, 15 deletions
diff --git a/board/miromico/hammerhead/hammerhead.c b/board/miromico/hammerhead/hammerhead.c
index d3875f4..8b3e22c 100644
--- a/board/miromico/hammerhead/hammerhead.c
+++ b/board/miromico/hammerhead/hammerhead.c
@@ -22,17 +22,15 @@
* MA 02111-1307 USA
*/
-#include "../cpu/at32ap/at32ap700x/sm.h"
-
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/sdram.h>
#include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/hmatrix.h>
#include <asm/arch/memory-map.h>
+#include <asm/arch/portmux.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -64,14 +62,14 @@ int board_early_init_f(void)
/* Enable SDRAM in the EBI mux */
hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
- gpio_enable_ebi();
- gpio_enable_usart1();
+ portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH);
+ portmux_enable_usart1(PORTMUX_DRIVE_MIN);
#if defined(CONFIG_MACB)
- gpio_enable_macb0();
+ portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
#endif
#if defined(CONFIG_MMC)
- gpio_enable_mmci();
+ portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
#endif
return 0;
}
@@ -96,18 +94,16 @@ phys_size_t initdram(int board_type)
return actual_size;
}
-void board_init_info(void)
+int board_early_init_r(void)
{
gd->bd->bi_phy_id[0] = 0x01;
+ return 0;
}
-void gclk_init(void)
+int board_postclk_init(void)
{
/* Hammerhead boards uses GCLK3 as 25MHz output to ethernet PHY */
-
- /* Select GCLK3 peripheral function */
- gpio_select_periph_A(GPIO_PIN_PB29, 0);
-
- /* Enable GCLK3 with no input divider, from OSC0 (crystal) */
- sm_writel(PM_GCCTRL(3), SM_BIT(CEN));
+ gclk_enable_output(3, PORTMUX_DRIVE_LOW);
+ gclk_set_rate(3, GCLK_PARENT_OSC0, 25000000);
+ return 0;
}