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| author | Eric Nelson <eric@nelint.com> | 2016-10-30 16:33:48 -0700 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2016-11-29 16:40:12 +0100 |
| commit | 7f17fb7400ff091dd48f86977655c6a57d06b17c (patch) | |
| tree | 3fffa58f57820093a9c8877e09d52602d830f03e /board/kosagi/novena | |
| parent | b33f74ead4dfd1ec0b500dc3d1cfef0e308b45c3 (diff) | |
| download | u-boot-imx-7f17fb7400ff091dd48f86977655c6a57d06b17c.zip u-boot-imx-7f17fb7400ff091dd48f86977655c6a57d06b17c.tar.gz u-boot-imx-7f17fb7400ff091dd48f86977655c6a57d06b17c.tar.bz2 | |
mx6: ddr: pass mx6_ddr_sysinfo to calibration routines
The DDR calibration routines have scattered support for bus
widths other than 64-bits:
-- The mmdc_do_write_level_calibration() routine assumes the
presence of PHY1, and
-- The mmdc_do_dqs_calibration() routine tries to determine
whether one or two DDR PHYs are active by reading MDCTL.
Since a caller of these routines must have a valid struct mx6_ddr_sysinfo
for use in calling mx6_dram_cfg(), and the bus width is available in the
"dsize" field, use this structure to inform the calibration routines which
PHYs are active.
This allows the use of the DDR calibration routines on CPU variants
like i.MX6SL that only have a single MMDC port.
Signed-off-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'board/kosagi/novena')
| -rw-r--r-- | board/kosagi/novena/novena_spl.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/board/kosagi/novena/novena_spl.c b/board/kosagi/novena/novena_spl.c index 92c61ae..b934d36 100644 --- a/board/kosagi/novena/novena_spl.c +++ b/board/kosagi/novena/novena_spl.c @@ -605,8 +605,8 @@ void board_init_f(ulong dummy) /* Perform DDR DRAM calibration */ udelay(100); - mmdc_do_write_level_calibration(); - mmdc_do_dqs_calibration(); + mmdc_do_write_level_calibration(&novena_ddr_info); + mmdc_do_dqs_calibration(&novena_ddr_info); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); |