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authorTom Rini <trini@ti.com>2014-08-04 13:35:50 -0400
committerTom Rini <trini@ti.com>2014-08-06 08:38:18 -0400
commitdcdb61a084bd3840d0987a5d01ae506c11efca1b (patch)
tree576fed73a7425aff29b2833ea7a132a1fc373c43 /board/keymile/kmp204x
parentaa159e681ec22a19ee4dd68ad4ec08b748e14d10 (diff)
parente3917b21c05776b41663bdfcc7666aca11a381a0 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'board/keymile/kmp204x')
-rw-r--r--board/keymile/kmp204x/kmp204x.c15
-rw-r--r--board/keymile/kmp204x/kmp204x.h7
-rw-r--r--board/keymile/kmp204x/qrio.c32
3 files changed, 54 insertions, 0 deletions
diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c
index 6bc8eb8..cd08379 100644
--- a/board/keymile/kmp204x/kmp204x.c
+++ b/board/keymile/kmp204x/kmp204x.c
@@ -80,14 +80,29 @@ int get_scl(void)
#define ZL30158_RST 8
#define BFTIC4_RST 0
+#define RSTRQSR1_WDT_RR 0x00200000
+#define RSTRQSR1_SW_RR 0x00100000
int board_early_init_f(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ bool cpuwd_flag = false;
+
+ /* configure mode for uP reset request */
+ qrio_uprstreq(UPREQ_CORE_RST);
/* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
setbits_be32(&gur->ddrclkdr, 0x001f000f);
+ /* set reset reason according CPU register */
+ if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) ==
+ RSTRQSR1_WDT_RR)
+ cpuwd_flag = true;
+
+ qrio_cpuwd_flag(cpuwd_flag);
+ /* clear CPU bits by writing 1 */
+ setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR);
+
/* set the BFTIC's prstcfg to reset at power-up and unit reset only */
qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
/* and enable WD on it */
diff --git a/board/keymile/kmp204x/kmp204x.h b/board/keymile/kmp204x/kmp204x.h
index afede99..e90e8ab 100644
--- a/board/keymile/kmp204x/kmp204x.h
+++ b/board/keymile/kmp204x/kmp204x.h
@@ -24,5 +24,12 @@ void qrio_wdmask(u8 bit, bool wden);
void qrio_prstcfg(u8 bit, u8 mode);
void qrio_set_leds(void);
void qrio_enable_app_buffer(void);
+void qrio_cpuwd_flag(bool flag);
+int qrio_reset_reason(void);
+
+#define UPREQ_UNIT_RST 0x0
+#define UPREQ_CORE_RST 0x1
+
+void qrio_uprstreq(u8 mode);
void pci_of_setup(void *blob, bd_t *bd);
diff --git a/board/keymile/kmp204x/qrio.c b/board/keymile/kmp204x/qrio.c
index b6ba93a..edf3bf1 100644
--- a/board/keymile/kmp204x/qrio.c
+++ b/board/keymile/kmp204x/qrio.c
@@ -173,3 +173,35 @@ void qrio_enable_app_buffer(void)
ctrll |= (CTRLL_WRB_BUFENA);
out_8(qrio_base + CTRLL_OFF, ctrll);
}
+
+#define REASON1_OFF 0x12
+#define REASON1_CPUWD 0x01
+
+void qrio_cpuwd_flag(bool flag)
+{
+ u8 reason1;
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+ reason1 = in_8(qrio_base + REASON1_OFF);
+ if (flag)
+ reason1 |= REASON1_CPUWD;
+ else
+ reason1 &= ~REASON1_CPUWD;
+ out_8(qrio_base + REASON1_OFF, reason1);
+}
+
+#define RSTCFG_OFF 0x11
+
+void qrio_uprstreq(u8 mode)
+{
+ u32 rstcfg;
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+ rstcfg = in_8(qrio_base + RSTCFG_OFF);
+
+ if (mode & UPREQ_CORE_RST)
+ rstcfg |= UPREQ_CORE_RST;
+ else
+ rstcfg &= ~UPREQ_CORE_RST;
+
+ out_8(qrio_base + RSTCFG_OFF, rstcfg);
+}