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authorPaul Burton <paul.burton@imgtec.com>2015-01-29 10:38:20 +0000
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>2015-01-29 13:11:02 +0100
commitba21a453a58fc02b890f4064b293b1cb09fe7484 (patch)
tree0d58a392c462c7ebf135a1286e97e051d2391158 /board/imgtec
parent8755d50706742e4d302a335f4e69dd6430ec12a2 (diff)
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malta: IDE support
This patch adds IDE support to the MIPS Malta board. The IDE controller is enabled after probing the PCI bus and otherwise just makes use of U-boot generic IDE support. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Diffstat (limited to 'board/imgtec')
-rw-r--r--board/imgtec/malta/malta.c19
1 files changed, 19 insertions, 0 deletions
diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c
index 78c4bd4..72b03ff 100644
--- a/board/imgtec/malta/malta.c
+++ b/board/imgtec/malta/malta.c
@@ -6,6 +6,7 @@
*/
#include <common.h>
+#include <ide.h>
#include <netdev.h>
#include <pci.h>
#include <pci_gt64120.h>
@@ -217,4 +218,22 @@ void pci_init_board(void)
pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8);
val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT;
pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8);
+
+ bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_82371AB, 0);
+ if (bdf == -1)
+ panic("Failed to find PIIX4 IDE controller\n");
+
+ /* enable bus master & IO access */
+ val32 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
+ pci_write_config_dword(bdf, PCI_COMMAND, val32);
+
+ /* set latency */
+ pci_write_config_byte(bdf, PCI_LATENCY_TIMER, 0x40);
+
+ /* enable IDE/ATA */
+ pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_PRI,
+ PCI_CFG_PIIX4_IDETIM_IDE);
+ pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_SEC,
+ PCI_CFG_PIIX4_IDETIM_IDE);
}