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authorStephen Warren <swarren@nvidia.com>2015-10-05 16:58:52 -0600
committerTom Warren <twarren@nvidia.com>2015-11-12 09:21:04 -0700
commitdfa551e49c072b9f4e1b0486a4091cd80733733b (patch)
tree05c8b22da5b2a9a4f7251948d98cdecb0b0886ec /board/ifm
parent038be18fd95aa6283eafb85ceabc0b880976424b (diff)
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ARM: tegra210: implement PLLE init procedure from TRM
Implement the procedure that the TRM mandates to initialize PLLREFE and PLLE. This makes the PLL actually lock. Note that this section of the TRM is being cleaned up to remove some confusion. The set of register accesses in this patch should be final, although the step numbers/descriptions might still change. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
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