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authorAkshay Saraswat <akshay.s@samsung.com>2015-02-20 13:27:14 +0530
committerMinkyu Kang <mk7.kang@samsung.com>2015-02-28 18:03:46 +0900
commita389531439a7d5cea2829054edcf438dc76e79a9 (patch)
treeeb3579513553a870fac0ec44e5f9b6db0d88ef53 /board/hale
parent0c08baf05317c723214ba6e0ba89e4a4d9e0d3f1 (diff)
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Exynos542x: Add workaround for ARM errata 799270
This patch adds workaround for the ARM errata 799270 which says "If the L2 cache logic clock is stopped because of L2 inactivity, setting or clearing the ACTLR.SMP bit might not be effective. The bit is modified in the ACTLR, meaning a read of the register returns the updated value. However the logic that uses that bit retains the previous value." Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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