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author | Fabio Estevam <fabio.estevam@freescale.com> | 2014-11-14 09:37:00 -0200 |
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committer | Stefano Babic <sbabic@denx.de> | 2014-11-20 10:13:54 +0100 |
commit | e25fbe3fe531029dc7b100ea4c79dbc802e17fc2 (patch) | |
tree | 599241a4c86c6ea13c2f0ee671e191b3aedb432c /board/gateworks/gw_ventana/gw_ventana_spl.c | |
parent | 6e9b6bb5a06abd0b45da7f78d1ebb630e0e97fd0 (diff) | |
download | u-boot-imx-e25fbe3fe531029dc7b100ea4c79dbc802e17fc2.zip u-boot-imx-e25fbe3fe531029dc7b100ea4c79dbc802e17fc2.tar.gz u-boot-imx-e25fbe3fe531029dc7b100ea4c79dbc802e17fc2.tar.bz2 |
gw_ventana: Move the DCD settings to spl code
mx6sabresd_spl.cfg configures CCM registers, GPR registers and CCM_CCOSR.
Move the configuration to the spl code.
CCM_CCOSR setting is no longer required to get audio functionality in the
kernel, so remove such setting.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'board/gateworks/gw_ventana/gw_ventana_spl.c')
-rw-r--r-- | board/gateworks/gw_ventana/gw_ventana_spl.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index ca35b3c..d6a5847 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -8,6 +8,7 @@ #include <common.h> #include <i2c.h> #include <asm/io.h> +#include <asm/arch/crm_regs.h> #include <asm/arch/iomux.h> #include <asm/arch/mx6-ddr.h> #include <asm/arch/mx6-pins.h> @@ -392,6 +393,30 @@ static void spl_dram_init(int width, int size_mb, int board_model) mx6_dram_cfg(&sysinfo, calib, mem); } +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0x00FFF300, &ccm->CCGR4); + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); +} + +static void gpr_init(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* enable AXI cache for VDOA/VPU/IPU */ + writel(0xF00000CF, &iomux->gpr[4]); + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ + writel(0x007F007F, &iomux->gpr[6]); + writel(0x007F007F, &iomux->gpr[7]); +} + /* * called from C runtime startup code (arch/arm/lib/crt0.S:_main) * - we have a stack and a place to store GD, both in SRAM @@ -405,6 +430,9 @@ void board_init_f(ulong dummy) /* setup AIPS and disable watchdog */ arch_cpu_init(); + ccgr_init(); + gpr_init(); + /* iomux and setup of i2c */ board_early_init_f(); i2c_setup_iomux(); |