diff options
| author | Tim Harvey <tharvey@gateworks.com> | 2014-03-06 07:46:30 -0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2014-03-12 10:23:03 +0100 |
| commit | 59189a8b26793ace1b7d0eee9496875ac8713299 (patch) | |
| tree | 1ef0c4d4ba8a38443900ff20b22ed4bb4dc44ab7 /board/gateworks/gw_ventana/clocks.cfg | |
| parent | 1ad6364eeb4f578e423081d1748e8a3fdf1ab01d (diff) | |
| download | u-boot-imx-59189a8b26793ace1b7d0eee9496875ac8713299.zip u-boot-imx-59189a8b26793ace1b7d0eee9496875ac8713299.tar.gz u-boot-imx-59189a8b26793ace1b7d0eee9496875ac8713299.tar.bz2 | |
ventana: Add Gateworks Ventana family support
Gateworks Ventana is a product family based on the i.MX6. This
patch adds support for all boards in the Ventana family. Where
possible, data from the boards EEPROM is used to determine various
details about the board at runtime.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Diffstat (limited to 'board/gateworks/gw_ventana/clocks.cfg')
| -rw-r--r-- | board/gateworks/gw_ventana/clocks.cfg | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/board/gateworks/gw_ventana/clocks.cfg b/board/gateworks/gw_ventana/clocks.cfg new file mode 100644 index 0000000..a8118a2 --- /dev/null +++ b/board/gateworks/gw_ventana/clocks.cfg @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2013 Gateworks Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */ +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 --> CKO1 enabled + * cko1_div = 111 --> divide by 8 + * cko1_sel = 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ +DATA 4, CCM_CCOSR, 0x000000fb |