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author | Anson Huang <b20788@freescale.com> | 2015-09-15 00:27:29 +0800 |
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committer | Anson Huang <b20788@freescale.com> | 2015-09-15 18:54:55 +0800 |
commit | df4df39ba304f25e751f1452b807161ef0b00eb3 (patch) | |
tree | e53a242c0d34dbd9d0786dda4e39833283420047 /board/freescale | |
parent | ef4cb7c53418e4e1dd7cfcb7c6974cfea77ef3c0 (diff) | |
download | u-boot-imx-df4df39ba304f25e751f1452b807161ef0b00eb3.zip u-boot-imx-df4df39ba304f25e751f1452b807161ef0b00eb3.tar.gz u-boot-imx-df4df39ba304f25e751f1452b807161ef0b00eb3.tar.bz2 |
MLK-11548 imx: imx6qp: add SabreSD board support
Add i.MX6QP SabreSD board support.
Signed-off-by: Anson Huang <b20788@freescale.com>
Diffstat (limited to 'board/freescale')
-rw-r--r-- | board/freescale/mx6sabresd/mx6qp.cfg | 155 | ||||
-rw-r--r-- | board/freescale/mx6sabresd/mx6sabresd.c | 8 |
2 files changed, 163 insertions, 0 deletions
diff --git a/board/freescale/mx6sabresd/mx6qp.cfg b/board/freescale/mx6sabresd/mx6qp.cfg new file mode 100644 index 0000000..13d54a1 --- /dev/null +++ b/board/freescale/mx6sabresd/mx6qp.cfg @@ -0,0 +1,155 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include <config.h> +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of spi, sd, sata + * the board has no nand and eimnor + * spinor: flash_offset: 0x0400 + * sata: flash_offset: 0x0400 + * sd/mmc: flash_offset: 0x0400 + */ + +/* the same flash_offset as sd */ +BOOT_FROM sd + +#ifdef CONFIG_USE_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sabresd/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4, 0x020e0798, 0x000c0000 +DATA 4, 0x020e0758, 0x00000000 +DATA 4, 0x020e0588, 0x00000030 +DATA 4, 0x020e0594, 0x00000030 +DATA 4, 0x020e056c, 0x00000030 +DATA 4, 0x020e0578, 0x00000030 +DATA 4, 0x020e074c, 0x00000030 +DATA 4, 0x020e057c, 0x00000030 +DATA 4, 0x020e058c, 0x00000000 +DATA 4, 0x020e059c, 0x00000030 +DATA 4, 0x020e05a0, 0x00000030 +DATA 4, 0x020e078c, 0x00000030 +DATA 4, 0x020e0750, 0x00020000 +DATA 4, 0x020e05a8, 0x00000030 +DATA 4, 0x020e05b0, 0x00000030 +DATA 4, 0x020e0524, 0x00000030 +DATA 4, 0x020e051c, 0x00000030 +DATA 4, 0x020e0518, 0x00000030 +DATA 4, 0x020e050c, 0x00000030 +DATA 4, 0x020e05b8, 0x00000030 +DATA 4, 0x020e05c0, 0x00000030 +DATA 4, 0x020e0774, 0x00020000 +DATA 4, 0x020e0784, 0x00000030 +DATA 4, 0x020e0788, 0x00000030 +DATA 4, 0x020e0794, 0x00000030 +DATA 4, 0x020e079c, 0x00000030 +DATA 4, 0x020e07a0, 0x00000030 +DATA 4, 0x020e07a4, 0x00000030 +DATA 4, 0x020e07a8, 0x00000030 +DATA 4, 0x020e0748, 0x00000030 +DATA 4, 0x020e05ac, 0x00000030 +DATA 4, 0x020e05b4, 0x00000030 +DATA 4, 0x020e0528, 0x00000030 +DATA 4, 0x020e0520, 0x00000030 +DATA 4, 0x020e0514, 0x00000030 +DATA 4, 0x020e0510, 0x00000030 +DATA 4, 0x020e05bc, 0x00000030 +DATA 4, 0x020e05c4, 0x00000030 +DATA 4, 0x021b0800, 0xa1390003 +DATA 4, 0x021b080c, 0x001b001e +DATA 4, 0x021b0810, 0x002e0029 +DATA 4, 0x021b480c, 0x001b002a +DATA 4, 0x021b4810, 0x0019002c +DATA 4, 0x021b083c, 0x43240334 +DATA 4, 0x021b0840, 0x0324031a +DATA 4, 0x021b483c, 0x43340344 +DATA 4, 0x021b4840, 0x03280276 +DATA 4, 0x021b0848, 0x44383A3E +DATA 4, 0x021b4848, 0x3C3C3846 +DATA 4, 0x021b0850, 0x2e303230 +DATA 4, 0x021b4850, 0x38283E34 +DATA 4, 0x021b081c, 0x33333333 +DATA 4, 0x021b0820, 0x33333333 +DATA 4, 0x021b0824, 0x33333333 +DATA 4, 0x021b0828, 0x33333333 +DATA 4, 0x021b481c, 0x33333333 +DATA 4, 0x021b4820, 0x33333333 +DATA 4, 0x021b4824, 0x33333333 +DATA 4, 0x021b4828, 0x33333333 +DATA 4, 0x021b08c0, 0x24912492 +DATA 4, 0x021b48c0, 0x24912492 +DATA 4, 0x021b08b8, 0x00000800 +DATA 4, 0x021b48b8, 0x00000800 +DATA 4, 0x021b0004, 0x00020036 +DATA 4, 0x021b0008, 0x09444040 +DATA 4, 0x021b000c, 0x898E7955 +DATA 4, 0x021b0010, 0xFF328F64 +DATA 4, 0x021b0014, 0x01ff00db +DATA 4, 0x021b0018, 0x00001740 +DATA 4, 0x021b001c, 0x00008000 +DATA 4, 0x021b002c, 0x000026d2 +DATA 4, 0x021b0030, 0x008E1023 +DATA 4, 0x021b0040, 0x00000027 +DATA 4, 0x021b0400, 0x14420000 +DATA 4, 0x021b0000, 0x831A0000 +DATA 4, 0x00bb0008, 0x00000007 +DATA 4, 0x00bb000c, 0x2891E41A +DATA 4, 0x00bb0038, 0x00000564 +DATA 4, 0x00bb0014, 0x00000040 +DATA 4, 0x00bb0028, 0x00000020 +DATA 4, 0x00bb002c, 0x00000020 +DATA 4, 0x021b001c, 0x04088032 +DATA 4, 0x021b001c, 0x00008033 +DATA 4, 0x021b001c, 0x00048031 +DATA 4, 0x021b001c, 0x09408030 +DATA 4, 0x021b001c, 0x04008040 +DATA 4, 0x021b0020, 0x00005800 +DATA 4, 0x021b0818, 0x00011117 +DATA 4, 0x021b4818, 0x00011117 +DATA 4, 0x021b0004, 0x00025576 +DATA 4, 0x021b0404, 0x00011006 +DATA 4, 0x021b001c, 0x00000000 + +/* set the default clock gate to save power */ +DATA 4, 0x020c4068, 0x00C03F3F +DATA 4, 0x020c406c, 0x0030FC03 +DATA 4, 0x020c4070, 0x0FFFC000 +DATA 4, 0x020c4074, 0x3FF00000 +DATA 4, 0x020c4078, 0x00FFF300 +DATA 4, 0x020c407c, 0x0F0000F3 +DATA 4, 0x020c4080, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ +DATA 4, 0x020e0018, 0x77177717 +DATA 4, 0x020e001c, 0x77177717 +#endif diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index e145912..3e87c8e 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -1018,6 +1018,14 @@ int power_init_board(void) reg |= 0x40; pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg); + if (is_mx6dqp()) { + /* set SW2 staby volatage 0.975V*/ + pmic_reg_read(pfuze, PFUZE100_SW2STBY, ®); + reg &= ~0x3f; + reg |= 0x17; + pmic_reg_write(pfuze, PFUZE100_SW2STBY, reg); + } + return 0; } |