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authorAndy Fleming <afleming@freescale.com>2008-07-07 18:02:08 -0500
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2008-07-14 11:21:33 -0500
commitab5cda9f88c3eaf9cf599adc3a3375906c4ed904 (patch)
treea0a7f06b009be7401123cae043939722cc666f68 /board/freescale
parentd5996dd555edf52721b7691a4c59de016251ed39 (diff)
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Remove LBC_CACHE_BASE from 8544 DS
The 8544 DS doesn't have any cacheable Local Bus memories set up. By mapping space for some anyway, we were allowing speculative loads into unmapped space, which would cause an exception (annoying, even if ultimately harmless). Removing LBC_CACHE_BASE, and using LBC_NONCACHE_BASE for the LBC LAW solves the problem. Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/freescale')
-rw-r--r--board/freescale/mpc8544ds/law.c2
-rw-r--r--board/freescale/mpc8544ds/tlb.c12
2 files changed, 3 insertions, 11 deletions
diff --git a/board/freescale/mpc8544ds/law.c b/board/freescale/mpc8544ds/law.c
index a82dede..54cf36b 100644
--- a/board/freescale/mpc8544ds/law.c
+++ b/board/freescale/mpc8544ds/law.c
@@ -30,7 +30,7 @@
struct law_entry law_table[] = {
SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI),
- SET_LAW(CFG_LBC_CACHE_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC),
+ SET_LAW(CFG_LBC_NONCACHE_BASE, LAWAR_SIZE_128M, LAW_TRGT_IF_LBC),
SET_LAW(CFG_PCIE1_MEM_PHYS, LAWAR_SIZE_256M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
SET_LAW(CFG_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2),
diff --git a/board/freescale/mpc8544ds/tlb.c b/board/freescale/mpc8544ds/tlb.c
index 61fc609..40e0499 100644
--- a/board/freescale/mpc8544ds/tlb.c
+++ b/board/freescale/mpc8544ds/tlb.c
@@ -79,21 +79,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_64M, 1),
-#ifdef CFG_LBC_CACHE_BASE
/*
- * TLB 5: 64M Cacheable, non-guarded
- */
- SET_TLB_ENTRY(1, CFG_LBC_CACHE_BASE, CFG_LBC_CACHE_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 5, BOOKE_PAGESZ_64M, 1),
-#endif
- /*
- * TLB 6: 64M Non-cacheable, guarded
+ * TLB 5: 64M Non-cacheable, guarded
* 0xf8000000 64M PIXIS 0xF8000000 - 0xFBFFFFFF
*/
SET_TLB_ENTRY(1, CFG_LBC_NONCACHE_BASE, CFG_LBC_NONCACHE_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_64M, 1),
+ 0, 5, BOOKE_PAGESZ_64M, 1),
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);