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authorWolfgang Denk <wd@denx.de>2013-10-04 17:43:24 +0200
committerTom Rini <trini@ti.com>2013-10-14 16:06:54 -0400
commit93e1459641e758d2b096d3f1b39414a39bb314f8 (patch)
tree3780156a164d3924a2412354872203e4b46f8592 /board/freescale
parent3765b3e7bd0f8e46914d417f29cbcb0c72b1acf7 (diff)
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Coding Style cleanup: replace leading SPACEs by TABs
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Drop changes for PEP 4 following python tools] Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'board/freescale')
-rw-r--r--board/freescale/b4860qds/tlb.c2
-rw-r--r--board/freescale/bsc9132qds/README10
-rw-r--r--board/freescale/mpc8313erdb/mpc8313erdb.c4
-rw-r--r--board/freescale/mpc8360emds/mpc8360emds.c4
4 files changed, 10 insertions, 10 deletions
diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c
index f71aca4..00798a1 100644
--- a/board/freescale/b4860qds/tlb.c
+++ b/board/freescale/b4860qds/tlb.c
@@ -68,7 +68,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
0, 3, BOOKE_PAGESZ_256M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
- CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
+ CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
diff --git a/board/freescale/bsc9132qds/README b/board/freescale/bsc9132qds/README
index 4a3dbfe..f8377c9 100644
--- a/board/freescale/bsc9132qds/README
+++ b/board/freescale/bsc9132qds/README
@@ -23,14 +23,14 @@ Overview
ECC), up to 1333 MHz data rate
- Dedicated security engine featuring trusted boot
- Two DMA controllers
- - OCNDMA with four bidirectional channels
- - SysDMA with sixteen bidirectional channels
+ - OCNDMA with four bidirectional channels
+ - SysDMA with sixteen bidirectional channels
- Interfaces
- - Four-lane SerDes PHY
+ - Four-lane SerDes PHY
- PCI Express controller complies with the PEX Specification-Rev 2.0
- - Two Common Public Radio Interface (CPRI) controller lanes
+ - Two Common Public Radio Interface (CPRI) controller lanes
- High-speed USB 2.0 host and device controller with ULPI interface
- - Enhanced secure digital (SD/MMC) host controller (eSDHC)
+ - Enhanced secure digital (SD/MMC) host controller (eSDHC)
- Antenna interface controller (AIC), supporting four industry
standard JESD207/four custom ADI RF interfaces
- ADI lanes support both full duplex FDD support & half duplex TDD
diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c
index 591a4c6..69e98a5 100644
--- a/board/freescale/mpc8313erdb/mpc8313erdb.c
+++ b/board/freescale/mpc8313erdb/mpc8313erdb.c
@@ -129,12 +129,12 @@ void board_init_f(ulong bootflag)
{
board_early_init_f();
NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
- CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+ CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
puts("NAND boot... ");
init_timebase();
initdram(0);
relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
- CONFIG_SYS_NAND_U_BOOT_RELOC);
+ CONFIG_SYS_NAND_U_BOOT_RELOC);
}
void board_init_r(gd_t *gd, ulong dest_addr)
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c
index 39a86df..ac96163 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -427,7 +427,7 @@ void ft_board_setup(void *blob, bd_t *bd)
if (prop) {
path = fdt_path_offset(blob, prop);
prop = fdt_getprop(blob, path,
- "phy-connection-type", 0);
+ "phy-connection-type", 0);
if (prop && (strcmp(prop, "rgmii-id") == 0))
fdt_fixup_phy_connection(blob, path,
PHY_INTERFACE_MODE_RGMII_RXID);
@@ -439,7 +439,7 @@ void ft_board_setup(void *blob, bd_t *bd)
if (prop) {
path = fdt_path_offset(blob, prop);
prop = fdt_getprop(blob, path,
- "phy-connection-type", 0);
+ "phy-connection-type", 0);
if (prop && (strcmp(prop, "rgmii-id") == 0))
fdt_fixup_phy_connection(blob, path,
PHY_INTERFACE_MODE_RGMII_RXID);