Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

23 files changed, 367 insertions, 71 deletions

diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c
index 8148e46..56e4f63 100644
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -43,6 +43,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 1 */
 	/* *I*** - Covers boot page */
 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+
+#if !defined(CONFIG_SECURE_BOOT)
 	/*
 	 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
 	 * SRAM is at 0xfff00000, it covered the 0xfffff000.
@@ -50,6 +52,19 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+	/*
+	 * *I*G - L3SRAM. When L3 is used as 1M SRAM, in case of Secure Boot
+	 * the physical address of the SRAM is at CONFIG_SYS_INIT_L3_ADDR,
+	 * and virtual address is CONFIG_SYS_MONITOR_BASE
+	 */
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_MONITOR_BASE & 0xfff00000,
+			CONFIG_SYS_INIT_L3_ADDR & 0xfff00000,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 0, BOOKE_PAGESZ_1M, 1),
+#endif
+
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 	/*
 	 * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS
index 745847c..73b0553 100644
--- a/board/freescale/corenet_ds/MAINTAINERS
+++ b/board/freescale/corenet_ds/MAINTAINERS
@@ -28,3 +28,10 @@ F:	configs/P5040DS_NAND_defconfig
 F:	configs/P5040DS_SDCARD_defconfig
 F:	configs/P5040DS_SPIFLASH_defconfig
 F:	configs/P5040DS_SECURE_BOOT_defconfig
+
+CORENET_DS_SECURE_BOOT BOARD
+M:	Aneesh Bansal <aneesh.bansal@freescale.com>
+S:	Maintained
+F:	configs/P3041DS_NAND_SECURE_BOOT_defconfig
+F:	configs/P5020DS_NAND_SECURE_BOOT_defconfig
+F:	configs/P5040DS_NAND_SECURE_BOOT_defconfig
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 3f47cfb..61b7a91 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -428,8 +428,13 @@ int ft_board_setup(void *blob, bd_t *bd)
 {
 	phys_addr_t base;
 	phys_size_t size;
+#if defined(CONFIG_P1020RDB_PD) || defined(CONFIG_P1020RDB_PC)
 	const char *soc_usb_compat = "fsl-usb2-dr";
-	int err, usb1_off, usb2_off;
+	int usb_err, usb1_off, usb2_off;
+#endif
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+	int err;
+#endif
 
 	ft_cpu_setup(blob, bd);
 
@@ -473,6 +478,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 	}
 #endif
 
+#if defined(CONFIG_P1020RDB_PD) || defined(CONFIG_P1020RDB_PC)
 /* Delete USB2 node as it is muxed with eLBC */
 	usb1_off = fdt_node_offset_by_compatible(blob, -1,
 		soc_usb_compat);
@@ -488,11 +494,12 @@ int ft_board_setup(void *blob, bd_t *bd)
 		       soc_usb_compat);
 		return usb2_off;
 	}
-	err = fdt_del_node(blob, usb2_off);
-	if (err < 0) {
+	usb_err = fdt_del_node(blob, usb2_off);
+	if (usb_err < 0) {
 		printf("WARNING: could not remove %s\n", soc_usb_compat);
-		return err;
+		return usb_err;
 	}
+#endif
 
 	return 0;
 }
diff --git a/board/freescale/t102xqds/t1024_pbi.cfg b/board/freescale/t102xqds/t1024_pbi.cfg
index 7b9e9b0..98efca2 100644
--- a/board/freescale/t102xqds/t1024_pbi.cfg
+++ b/board/freescale/t102xqds/t1024_pbi.cfg
@@ -6,7 +6,7 @@
 #Configure CPC1 as 256KB SRAM
 09010100 00000000
 09010104 fffc0007
-09010f00 08000000
+09010f00 081e000d
 09010000 80000000
 #Configure LAW for CPC1
 09000cd0 00000000
diff --git a/board/freescale/t102xrdb/README b/board/freescale/t102xrdb/README
index 922450e..7d3794a 100644
--- a/board/freescale/t102xrdb/README
+++ b/board/freescale/t102xrdb/README
@@ -70,6 +70,7 @@ Deep Sleep:	yes    no
 I2C controller: 4      3
 DDR:		64-bit 32-bit
 IFC:		32-bit 28-bit
+Package:	23x23  19x19
 
 
 T1024RDB board Overview
@@ -192,7 +193,7 @@ Software configurations and board settings
 	on T1024RDB:
 	   set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
 	on T1023RDB:
-	   set SW1[1:8] = '00010110', SW2[1] = '0', SW3[4] = '0' for NOR boot
+	   set SW1[1:8] = '00010111', SW2[1] = '1', SW3[4] = '0' for NOR boot
 
    Switching between default bank0 and alternate bank4 on NOR flash
    To change boot source to vbank4:
@@ -200,7 +201,7 @@ Software configurations and board settings
 	via software:   run command 'cpld reset altbank' in u-boot.
 	via DIP-switch: set SW3[5:7] = '100'
    on T1023RDB:
-	via software:   run command 'gpio vbank4' in u-boot.
+	via software:   run command 'switch bank4' in u-boot.
 	via DIP-switch: set SW3[5:7] = '100'
 
    To change boot source to vbank0:
@@ -208,7 +209,7 @@ Software configurations and board settings
 	via software:   run command 'cpld reset' in u-boot.
 	via DIP-Switch: set SW3[5:7] = '000'
    on T1023RDB:
-	via software:   run command 'gpio vbank0' in u-boot.
+	via software:   run command 'switch bank0' in u-boot.
 	via DIP-switch: set SW3[5:7] = '000'
 
 2. NAND Boot:
@@ -219,7 +220,7 @@ Software configurations and board settings
 	=> tftp 1000000 u-boot-with-spl-pbl.bin
 	=> nand erase 0 $filesize
 	=> nand write 1000000 0 $filesize
-	set SW1[1:8] = '10001000', SW2[1] = '1', SW3[4] = '1' for NAND boot
+	set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
 
 3. SPI Boot:
    a. build PBL image for SPI boot
@@ -241,11 +242,14 @@ Software configurations and board settings
 	$ make
    b. program u-boot-with-spl-pbl.bin to SD/MMC card
 	=> tftp 1000000 u-boot-with-spl-pbl.bin
-	=> mmc write 1000000 8 0x800
+	=> mmc write 1000000 8 0x7f0
 	=> tftp 1000000 fsl_fman_ucode_t1024_xx.bin
 	=> mmc write 1000000 0x820 80
 	set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
 
+   SW3[3] = '1' for SD card(or 'switch sd' by software)
+   SW3[3] = '0' for eMMC (or 'switch emmc' by software)
+
 
 2-stage NAND/SPI/SD boot loader
 -------------------------------
@@ -292,7 +296,7 @@ Start		End		Definition	Size
 0x160000	0x17FFFF	FMAN Ucode	128KB
 
 
-SD Card memory Map on T1024RDB
+SD Card memory Map on T102xRDB
 ----------------------------------------------------
 Block		#blocks		Definition	Size
 0x008		2048		u-boot img	1MB
@@ -313,5 +317,5 @@ Start		End		Definition	Size
 0xa00000	0x3FFFFFF	rootfs		54MB
 
 
-For more details, please refer to T1024RDB Reference Manual
+For more details, please refer to T1024RDB/T1023RDB User Guide
 and Freescale QorIQ SDK Infocenter document.
diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c
index 1a3a996..9c581ff 100644
--- a/board/freescale/t102xrdb/spl.c
+++ b/board/freescale/t102xrdb/spl.c
@@ -30,6 +30,30 @@ unsigned long get_board_ddr_clk(void)
 	return CONFIG_DDR_CLK_FREQ;
 }
 
+#if defined(CONFIG_SPL_MMC_BOOT)
+#define GPIO1_SD_SEL 0x00020000
+int board_mmc_getcd(struct mmc *mmc)
+{
+	ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+	u32 val = in_be32(&pgpio->gpdat);
+
+	/* GPIO1_14, 0: eMMC, 1: SD */
+	val &= GPIO1_SD_SEL;
+
+	return val ? -1 : 1;
+}
+
+int board_mmc_getwp(struct mmc *mmc)
+{
+	ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+	u32 val = in_be32(&pgpio->gpdat);
+
+	val &= GPIO1_SD_SEL;
+
+	return val ? -1 : 0;
+}
+#endif
+
 void board_init_f(ulong bootflag)
 {
 	u32 plat_ratio, sys_clk, ccb_clk;
diff --git a/board/freescale/t102xrdb/t1023_rcw.cfg b/board/freescale/t102xrdb/t1023_rcw.cfg
index fa781d6..1d11a2e 100644
--- a/board/freescale/t102xrdb/t1023_rcw.cfg
+++ b/board/freescale/t102xrdb/t1023_rcw.cfg
@@ -4,5 +4,5 @@ aa55aa55 010e0100
 #Core/DDR: 1400Mhz/1600MT/s with single source clock
 0810000e 00000000 00000000 00000000
 3b800003 00000012 e8104000 21000000
-00000000 00000000 00000000 00020800
+00000000 00000000 00000000 00022800
 00000130 04020200 00000000 00000006
diff --git a/board/freescale/t102xrdb/t1024_pbi.cfg b/board/freescale/t102xrdb/t1024_pbi.cfg
index 7b9e9b0..98efca2 100644
--- a/board/freescale/t102xrdb/t1024_pbi.cfg
+++ b/board/freescale/t102xrdb/t1024_pbi.cfg
@@ -6,7 +6,7 @@
 #Configure CPC1 as 256KB SRAM
 09010100 00000000
 09010104 fffc0007
-09010f00 08000000
+09010f00 081e000d
 09010000 80000000
 #Configure LAW for CPC1
 09000cd0 00000000
diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c
index f971976..fddd240 100644
--- a/board/freescale/t102xrdb/t102xrdb.c
+++ b/board/freescale/t102xrdb/t102xrdb.c
@@ -20,6 +20,9 @@
 #include "t102xrdb.h"
 #ifdef CONFIG_T1024RDB
 #include "cpld.h"
+#elif defined(CONFIG_T1023RDB)
+#include <i2c.h>
+#include <mmc.h>
 #endif
 #include "../common/sleep.h"
 
@@ -27,13 +30,14 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_T1023RDB
 enum {
-	GPIO1_SD_SEL    = 0x00020000, /* GPIO1_14, 0: EMMC, 1:SD/MMC */
+	GPIO1_SD_SEL    = 0x00020000, /* GPIO1_14, 0: eMMC, 1:SD/MMC */
 	GPIO1_EMMC_SEL,
-	GPIO1_VBANK0,
-	GPIO1_VBANK4    = 0x00008000, /* GPIO1_16/20/22,  100:vBank4 */
-	GPIO1_VBANK_MASK = 0x00008a00,
-	GPIO1_DIR_OUTPUT = 0x00028a00,
-	GPIO1_GET_VAL,
+	GPIO3_GET_VERSION,	       /* GPIO3_4/5, 00:RevB, 01: RevC */
+	GPIO3_BRD_VER_MASK = 0x0c000000,
+	GPIO3_OFFSET = 0x2000,
+	I2C_GET_BANK,
+	I2C_SET_BANK0,
+	I2C_SET_BANK4,
 };
 #endif
 
@@ -48,9 +52,11 @@ int checkboard(void)
 	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 
 	printf("Board: %sRDB, ", cpu->name);
-#ifdef CONFIG_T1024RDB
+#if defined(CONFIG_T1024RDB)
 	printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
 	       CPLD_READ(hw_ver), CPLD_READ(sw_ver));
+#elif defined(CONFIG_T1023RDB)
+	printf("Rev%c, ", t1023rdb_ctrl(GPIO3_GET_VERSION) + 'B');
 #endif
 	printf("boot from ");
 
@@ -73,8 +79,7 @@ int checkboard(void)
 #ifdef CONFIG_NAND
 	puts("NAND\n");
 #else
-	printf("NOR vBank%d\n", (t1023rdb_gpio_ctrl(GPIO1_GET_VAL) &
-	       GPIO1_VBANK4) >> 15 ? 4 : 0);
+	printf("NOR vBank%d\n", t1023rdb_ctrl(I2C_GET_BANK));
 #endif
 #endif
 
@@ -196,64 +201,126 @@ int ft_board_setup(void *blob, bd_t *bd)
 	fdt_fixup_board_enet(blob);
 #endif
 
+#ifdef CONFIG_T1023RDB
+	if (t1023rdb_ctrl(GPIO3_GET_VERSION) > 0)
+		fdt_enable_nor(blob);
+#endif
+
 	return 0;
 }
 
-
 #ifdef CONFIG_T1023RDB
-static u32 t1023rdb_gpio_ctrl(u32 ctrl_type)
+/* Enable NOR flash for RevC */
+static void fdt_enable_nor(void *blob)
 {
-	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
-	u32 gpioval;
+	int nodeoff = fdt_node_offset_by_compatible(blob, 0, "cfi-flash");
+
+	if (nodeoff >= 0)
+		fdt_status_okay(blob, nodeoff);
+	else
+		printf("WARNING unable to set status for NOR\n");
+}
 
-	setbits_be32(&pgpio->gpdir, GPIO1_DIR_OUTPUT);
-	gpioval = in_be32(&pgpio->gpdat);
+int board_mmc_getcd(struct mmc *mmc)
+{
+	ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+	u32 val = in_be32(&pgpio->gpdat);
+
+	/* GPIO1_14, 0: eMMC, 1: SD/MMC */
+	val &= GPIO1_SD_SEL;
+
+	return val ? -1 : 1;
+}
+
+int board_mmc_getwp(struct mmc *mmc)
+{
+	ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+	u32 val = in_be32(&pgpio->gpdat);
+
+	val &= GPIO1_SD_SEL;
+
+	return val ? -1 : 0;
+}
+
+static u32 t1023rdb_ctrl(u32 ctrl_type)
+{
+	ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+	ccsr_gur_t __iomem  *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 val, orig_bus = i2c_get_bus_num();
+	u8 tmp;
 
 	switch (ctrl_type) {
 	case GPIO1_SD_SEL:
-		gpioval |= GPIO1_SD_SEL;
+		val = in_be32(&pgpio->gpdat);
+		val |= GPIO1_SD_SEL;
+		out_be32(&pgpio->gpdat, val);
+		setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
 		break;
 	case GPIO1_EMMC_SEL:
-		gpioval &= ~GPIO1_SD_SEL;
+		val = in_be32(&pgpio->gpdat);
+		val &= ~GPIO1_SD_SEL;
+		out_be32(&pgpio->gpdat, val);
+		setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
 		break;
-	case GPIO1_VBANK0:
-		gpioval &= ~GPIO1_VBANK_MASK;
+	case GPIO3_GET_VERSION:
+		pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
+			 + GPIO3_OFFSET);
+		val = in_be32(&pgpio->gpdat);
+		val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
+		if (val == 0x3) /* GPIO3_4/5 not used on RevB */
+			val = 0;
+		return val;
+	case I2C_GET_BANK:
+		i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
+		i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1);
+		tmp &= 0x7;
+		tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
+		i2c_set_bus_num(orig_bus);
+		return tmp;
+	case I2C_SET_BANK0:
+		i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
+		tmp = 0x0;
+		i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
+		tmp = 0xf8;
+		i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
+		/* asserting HRESET_REQ */
+		out_be32(&gur->rstcr, 0x2);
 		break;
-	case GPIO1_VBANK4:
-		gpioval &= ~GPIO1_VBANK_MASK;
-		gpioval |= GPIO1_VBANK4;
+	case I2C_SET_BANK4:
+		i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
+		tmp = 0x1;
+		i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
+		tmp = 0xf8;
+		i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
+		out_be32(&gur->rstcr, 0x2);
 		break;
-	case GPIO1_GET_VAL:
-		return gpioval;
 	default:
 		break;
 	}
-	out_be32(&pgpio->gpdat, gpioval);
-
 	return 0;
 }
 
-static int gpio_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
+static int switch_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 		    char * const argv[])
 {
 	if (argc < 2)
 		return CMD_RET_USAGE;
-	if (!strcmp(argv[1], "vbank0"))
-		t1023rdb_gpio_ctrl(GPIO1_VBANK0);
-	else if (!strcmp(argv[1], "vbank4"))
-		t1023rdb_gpio_ctrl(GPIO1_VBANK4);
+	if (!strcmp(argv[1], "bank0"))
+		t1023rdb_ctrl(I2C_SET_BANK0);
+	else if (!strcmp(argv[1], "bank4") || !strcmp(argv[1], "altbank"))
+		t1023rdb_ctrl(I2C_SET_BANK4);
 	else if (!strcmp(argv[1], "sd"))
-		t1023rdb_gpio_ctrl(GPIO1_SD_SEL);
-	else if (!strcmp(argv[1], "EMMC"))
-		t1023rdb_gpio_ctrl(GPIO1_EMMC_SEL);
+		t1023rdb_ctrl(GPIO1_SD_SEL);
+	else if (!strcmp(argv[1], "emmc"))
+		t1023rdb_ctrl(GPIO1_EMMC_SEL);
 	else
 		return CMD_RET_USAGE;
 	return 0;
 }
 
 U_BOOT_CMD(
-	gpio, 2, 0, gpio_cmd,
-	"for vbank0/vbank4/SD/eMMC switch control in runtime",
-	"command (e.g. gpio vbank4)"
+	switch, 2, 0, switch_cmd,
+	"for bank0/bank4/sd/emmc switch control in runtime",
+	"command (e.g. switch bank4)"
 );
 #endif
diff --git a/board/freescale/t102xrdb/t102xrdb.h b/board/freescale/t102xrdb/t102xrdb.h
index 3f5d85a..ae5c60f 100644
--- a/board/freescale/t102xrdb/t102xrdb.h
+++ b/board/freescale/t102xrdb/t102xrdb.h
@@ -10,6 +10,7 @@
 void fdt_fixup_board_enet(void *blob);
 void pci_of_setup(void *blob, bd_t *bd);
 #ifdef CONFIG_T1023RDB
-static u32 t1023rdb_gpio_ctrl(u32 ctrl_type);
+static u32 t1023rdb_ctrl(u32 ctrl_type);
+static void fdt_enable_nor(void *blob);
 #endif
 #endif
diff --git a/board/freescale/t1040qds/t1040_pbi.cfg b/board/freescale/t1040qds/t1040_pbi.cfg
index 10b1a6d..121b005 100644
--- a/board/freescale/t1040qds/t1040_pbi.cfg
+++ b/board/freescale/t1040qds/t1040_pbi.cfg
@@ -6,7 +6,7 @@
 #Configure CPC1 as 256KB SRAM
 09010100 00000000
 09010104 fffc0007
-09010f00 08000000
+09010f00 081e000d
 09010000 80000000
 #Configure LAW for CPC1
 09000cf0 00000000
diff --git a/board/freescale/t104xrdb/MAINTAINERS b/board/freescale/t104xrdb/MAINTAINERS
index 13d9be9..7597800 100644
--- a/board/freescale/t104xrdb/MAINTAINERS
+++ b/board/freescale/t104xrdb/MAINTAINERS
@@ -6,7 +6,13 @@ F:	include/configs/T104xRDB.h
 F:	configs/T1040RDB_defconfig
 F:	configs/T1040RDB_NAND_defconfig
 F:	configs/T1040RDB_SPIFLASH_defconfig
+F:	configs/T1040D4RDB_defconfig
+F:	configs/T1040D4RDB_NAND_defconfig
+F:	configs/T1040D4RDB_SPIFLASH_defconfig
 F:	configs/T1042RDB_defconfig
+F:	configs/T1042D4RDB_defconfig
+F:	configs/T1042D4RDB_NAND_defconfig
+F:	configs/T1042D4RDB_SPIFLASH_defconfig
 F:	configs/T1042RDB_PI_defconfig
 F:	configs/T1042RDB_PI_NAND_defconfig
 F:	configs/T1042RDB_PI_SPIFLASH_defconfig
@@ -15,10 +21,14 @@ T1040RDB_SDCARD BOARD
 #M:	-
 S:	Maintained
 F:	configs/T1040RDB_SDCARD_defconfig
+F:	configs/T1040D4RDB_SDCARD_defconfig
+F:	configs/T1042D4RDB_SDCARD_defconfig
 F:	configs/T1042RDB_PI_SDCARD_defconfig
 
 T1040RDB_SECURE_BOOT BOARD
 M:	Aneesh Bansal  <aneesh.bansal@freescale.com>
 S:	Maintained
 F:	configs/T1040RDB_SECURE_BOOT_defconfig
+F:	configs/T1040D4RDB_SECURE_BOOT_defconfig
 F:	configs/T1042RDB_SECURE_BOOT_defconfig
+F:	configs/T1042D4RDB_SECURE_BOOT_defconfig
diff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README
index ac95b5e..b9d2212 100644
--- a/board/freescale/t104xrdb/README
+++ b/board/freescale/t104xrdb/README
@@ -12,6 +12,17 @@ The T1042RDB_PI is a Freescale reference board that hosts the T1042 SoC.
 (a personality of T1040 SoC). The board is similar to T1040RDB but is
 designed specially with low power features targeted for Printing Image Market.
 
+The T1040D4RDB is a Freescale reference board that hosts the T1040 SoC.
+The board is re-designed T1040RDB board with following changes :
+    - Support of DDR4 memory and some enhancements
+
+The T1042D4RDB is a Freescale reference board that hosts the T1042 SoC.
+The board is re-designed T1040RDB board with following changes :
+    - Support of DDR4 memory
+    - Support for 0x86 serdes protocol which can support following interfaces
+        - 2 RGMII's on DTSEC4, DTSEC5
+        - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
+
 Basic difference's among T1040RDB, T1042RDB_PI, T1042RDB
 -------------------------------------------------------------------------
 Board		Si		Protocol		Targeted Market
@@ -19,6 +30,8 @@ Board		Si		Protocol		Targeted Market
 T1040RDB	T1040		0x66                    Networking
 T1040RDB	T1042		0x86                    Networking
 T1042RDB_PI	T1042		0x06                    Printing & Imaging
+T1040D4RDB	T1040		0x66                    Networking
+T1042D4RDB	T1042		0x86                    Networking
 
 
 T1040 SoC Overview
@@ -70,7 +83,6 @@ The T1040/T1042 SoC includes the following function and features:
 
 T1040 SoC Personalities
 -------------------------
-
 T1022 Personality:
 T1022 is a reduced personality of T1040 with less core/clusters.
 
@@ -268,8 +280,13 @@ SPI Flash memory Map on T104xRDB
 Please note QE Firmware is only valid for T1040RDB
 
 
-Switch Settings: (ON is 0, OFF is 1)
-===============
+Switch Settings for T104xRDB boards: (ON is 0, OFF is 1)
+==========================================================
+NOR boot SW setting:
+SW1: 00010011
+SW2: 10111011
+SW3: 11100001
+
 NAND boot SW setting:
 SW1: 10001000
 SW2: 00111011
@@ -284,3 +301,67 @@ SD boot SW setting:
 SW1: 00100000
 SW2: 00111011
 SW3: 11100001
+
+Switch Settings for T104xD4RDB boards: (ON is 0, OFF is 1)
+=============================================================
+NOR boot SW setting:
+SW1: 00010011
+SW2: 10111001
+SW3: 11100001
+
+NAND boot SW setting:
+SW1: 10001000
+SW2: 00111001
+SW3: 11110001
+
+SPI boot SW setting:
+SW1: 00100010
+SW2: 10111001
+SW3: 11100001
+
+SD boot SW setting:
+SW1: 00100000
+SW2: 00111001
+SW3: 11100001
+
+PBL-based image generation
+==========================
+Changes only the required register bit in in PBI commands.
+
+Provides reference code which might needs some
+modification as per requirement.
+example:
+By default PBI_SRC=14 (which is for IFC-NAND/NOR) in rcw.cfg file
+which needs to be changed for SPI and SD.
+
+For SD-boot
+==============
+1. Set RCW[192:195], PBI_SRC bits as 6 in RCW file (t1040d4_rcw.cfg type files)
+
+example:
+ RCW file: board/freescale/t104xrdb/t1040d4_rcw.cfg
+
+Change
+66000002 40000002 ec027000 01000000
+to
+66000002 40000002 6c027000 01000000
+
+2. SD does not support flush so remove flush from pbl, make changes in
+   tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000
+   with 0x091380c0
+
+For SPI-boot
+==============
+1. Set RCW[192:195], PBI_SRC bits as 5 in RCW file (t1040d4_rcw.cfg type files)
+
+example:
+ RCW file: board/freescale/t104xrdb/t1040d4_rcw.cfg
+
+Change
+66000002 40000002 ec027000 01000000
+to
+66000002 40000002 5c027000 01000000
+
+2. SPI does not support flush so remove flush from pbl, make changes in
+   tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000
+   with 0x091380c0
diff --git a/board/freescale/t104xrdb/cpld.c b/board/freescale/t104xrdb/cpld.c
index df0e348..0ce4e47 100644
--- a/board/freescale/t104xrdb/cpld.c
+++ b/board/freescale/t104xrdb/cpld.c
@@ -69,7 +69,11 @@ static void cpld_dump_regs(void)
 	printf("int_status	 = 0x%02x\n", CPLD_READ(int_status));
 	printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status));
 	printf("fan_ctl_status	 = 0x%02x\n", CPLD_READ(fan_ctl_status));
+#if defined(CONFIG_T104XD4RDB)
+	printf("int_mask	 = 0x%02x\n", CPLD_READ(int_mask));
+#else
 	printf("led_ctl_status	 = 0x%02x\n", CPLD_READ(led_ctl_status));
+#endif
 	printf("sfp_ctl_status	 = 0x%02x\n", CPLD_READ(sfp_ctl_status));
 	printf("misc_ctl_status	 = 0x%02x\n", CPLD_READ(misc_ctl_status));
 	printf("boot_override	 = 0x%02x\n", CPLD_READ(boot_override));
diff --git a/board/freescale/t104xrdb/cpld.h b/board/freescale/t104xrdb/cpld.h
index 0da9a01..2fb4105 100644
--- a/board/freescale/t104xrdb/cpld.h
+++ b/board/freescale/t104xrdb/cpld.h
@@ -21,7 +21,11 @@ struct cpld_data {
 	u8 int_status;		/* 0x12 - Interrupt status Register */
 	u8 flash_ctl_status;	/* 0x13 - Flash control and status register */
 	u8 fan_ctl_status;	/* 0x14 - Fan control and status register  */
+#if defined(CONFIG_T104XD4RDB)
+	u8 int_mask;		/* 0x15 - Interrupt mask Register */
+#else
 	u8 led_ctl_status;	/* 0x15 - LED control and status register */
+#endif
 	u8 sfp_ctl_status;	/* 0x16 - SFP control and status register  */
 	u8 misc_ctl_status;	/* 0x17 - Miscellanies ctrl & status register*/
 	u8 boot_override;	/* 0x18 - Boot override register */
@@ -38,3 +42,5 @@ void cpld_write(unsigned int reg, u8 value);
 #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
 #define CPLD_WRITE(reg, value)\
 		cpld_write(offsetof(struct cpld_data, reg), value)
+#define MISC_CTL_SG_SEL		0x80
+#define MISC_CTL_AURORA_SEL	0x02
diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c
index e1148e5..cf79d2d 100644
--- a/board/freescale/t104xrdb/ddr.c
+++ b/board/freescale/t104xrdb/ddr.c
@@ -75,7 +75,11 @@ found:
 	 * Factors to consider for half-strength driver enable:
 	 *	- number of DIMMs installed
 	 */
+#ifdef CONFIG_SYS_FSL_DDR4
+	popts->half_strength_driver_enable = 1;
+#else
 	popts->half_strength_driver_enable = 0;
+#endif
 	/*
 	 * Write leveling override
 	 */
@@ -91,8 +95,14 @@ found:
 	popts->zq_en = 1;
 
 	/* DHC_EN =1, ODT = 75 Ohm */
+#ifdef CONFIG_SYS_FSL_DDR4
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_120OHM);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_120OHM) |
+		DDR_CDR2_VREF_OVRD(70);       /* Vref = 70% */
+#else
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
 	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+#endif
 }
 
 #if defined(CONFIG_DEEP_SLEEP)
diff --git a/board/freescale/t104xrdb/ddr.h b/board/freescale/t104xrdb/ddr.h
index ab1c32d..b9c02f7 100644
--- a/board/freescale/t104xrdb/ddr.h
+++ b/board/freescale/t104xrdb/ddr.h
@@ -28,6 +28,9 @@ static const struct board_specific_parameters udimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2
 	 */
+#ifdef CONFIG_SYS_FSL_DDR4
+	{2,  1600, 4, 4,     6, 0x07090A0c, 0x0e0f100a},
+#elif defined(CONFIG_SYS_FSL_DDR3)
 	{2,  833,  4, 4,     6, 0x06060607, 0x08080807},
 	{2,  833,  0, 4,     6, 0x06060607, 0x08080807},
 	{2,  1350, 4, 4,     7, 0x0708080A, 0x0A0B0C09},
@@ -40,10 +43,14 @@ static const struct board_specific_parameters udimm0[] = {
 	{1,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09},
 	{1,  1666, 4, 4,     7, 0x0808090B, 0x0C0D0E0A},
 	{1,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A},
+#else
+#error DDR type not defined
+#endif
 	{}
 };
 
+#endif
+
 static const struct board_specific_parameters *udimms[] = {
 	udimm0,
 };
-#endif
diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c
index 7581a4cd..71d0457 100644
--- a/board/freescale/t104xrdb/eth.c
+++ b/board/freescale/t104xrdb/eth.c
@@ -43,9 +43,11 @@ int board_eth_init(bd_t *bis)
 		int idx = i - FM1_DTSEC1;
 
 		switch (fm_info_get_enet_if(i)) {
-#ifdef CONFIG_T1040RDB
+#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB)
 		case PHY_INTERFACE_MODE_SGMII:
-			/* T1040RDB only supports SGMII on DTSEC3 */
+			/* T1040RDB & T1040D4RDB only supports SGMII on
+			 * DTSEC3
+			 */
 			fm_info_set_phy_address(FM1_DTSEC3,
 						CONFIG_SYS_SGMII1_PHY_ADDR);
 			break;
@@ -60,6 +62,20 @@ int board_eth_init(bd_t *bis)
 						CONFIG_SYS_SGMII1_PHY_ADDR);
 			break;
 #endif
+#ifdef CONFIG_T1042D4RDB
+		case PHY_INTERFACE_MODE_SGMII:
+			/* T1042D4RDB supports SGMII on DTSEC1, DTSEC2
+			 *  & DTSEC3
+			 */
+			if (FM1_DTSEC1 == i)
+				phy_addr = CONFIG_SYS_SGMII1_PHY_ADDR;
+			if (FM1_DTSEC2 == i)
+				phy_addr = CONFIG_SYS_SGMII2_PHY_ADDR;
+			if (FM1_DTSEC3 == i)
+				phy_addr = CONFIG_SYS_SGMII3_PHY_ADDR;
+			fm_info_set_phy_address(i, phy_addr);
+			break;
+#endif
 		case PHY_INTERFACE_MODE_RGMII:
 			if (FM1_DTSEC4 == i)
 				phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
diff --git a/board/freescale/t104xrdb/t1040d4_rcw.cfg b/board/freescale/t104xrdb/t1040d4_rcw.cfg
new file mode 100644
index 0000000..c1034b3
--- /dev/null
+++ b/board/freescale/t104xrdb/t1040d4_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x66
+0c18000e 0e000000 00000000 00000000
+66000002 40000002 ec027000 01000000
+00000000 00000000 00000000 00030810
+00000000 0342580f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1042d4_rcw.cfg b/board/freescale/t104xrdb/t1042d4_rcw.cfg
new file mode 100644
index 0000000..9e0ee27
--- /dev/null
+++ b/board/freescale/t104xrdb/t1042d4_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x86
+0c18000e 0e000000 00000000 00000000
+86000002 40000002 ec027000 01000000
+00000000 00000000 00000000 00030810
+00000000 0342500f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t104x_pbi.cfg b/board/freescale/t104xrdb/t104x_pbi.cfg
index b83b9b7..51945b4 100644
--- a/board/freescale/t104xrdb/t104x_pbi.cfg
+++ b/board/freescale/t104xrdb/t104x_pbi.cfg
@@ -16,7 +16,7 @@
 #Configure CPC1 as 256KB SRAM
 09010100 00000000
 09010104 fffc0007
-09010f00 08000000
+09010f00 081e000d
 09010000 80000000
 #Configure LAW for CPC1
 09000cd0 00000000
diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c
index 9cd5e15..d982dfc 100644
--- a/board/freescale/t104xrdb/t104xrdb.c
+++ b/board/freescale/t104xrdb/t104xrdb.c
@@ -28,17 +28,18 @@ int checkboard(void)
 	struct cpu_type *cpu = gd->arch.cpu;
 	u8 sw;
 
+#ifdef CONFIG_T104XD4RDB
+	printf("Board: %sD4RDB\n", cpu->name);
+#else
 	printf("Board: %sRDB\n", cpu->name);
+#endif
 	printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
 	       CPLD_READ(hw_ver), CPLD_READ(sw_ver));
 
 	sw = CPLD_READ(flash_ctl_status);
 	sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
 
-	if (sw <= 7)
-		printf("vBank: %d\n", sw);
-	else
-		printf("Unsupported Bank=%x\n", sw);
+	printf("vBank: %d\n", sw);
 
 	return 0;
 }
@@ -91,6 +92,34 @@ int board_early_init_r(void)
 
 int misc_init_r(void)
 {
+	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 srds_s1;
+
+	srds_s1 = in_be32(&gur->rcwsr[4]) >> 24;
+
+	printf("SERDES Reference : 0x%X\n", srds_s1);
+
+	/* select SGMII*/
+	if (srds_s1 == 0x86)
+		CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
+					 MISC_CTL_SG_SEL);
+
+	/* select SGMII and Aurora*/
+	if (srds_s1 == 0x8E)
+		CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
+					 MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL);
+
+#if defined(CONFIG_T1040D4RDB)
+	/* Mask all CPLD interrupt sources, except QSGMII interrupts */
+	if (CPLD_READ(sw_ver) < 0x03) {
+		debug("CPLD SW version 0x%02x doesn't support int_mask\n",
+		      CPLD_READ(sw_ver));
+	} else {
+		CPLD_WRITE(int_mask, CPLD_INT_MASK_ALL &
+			   ~(CPLD_INT_MASK_QSGMII1 | CPLD_INT_MASK_QSGMII2));
+	}
+#endif
+
 	return 0;
 }
 
diff --git a/board/freescale/t4rdb/cpld.c b/board/freescale/t4rdb/cpld.c
index d5f3812..d563d0d 100644
--- a/board/freescale/t4rdb/cpld.c
+++ b/board/freescale/t4rdb/cpld.c
@@ -47,14 +47,8 @@ void cpld_set_altbank(void)
 
 	switch (curbank) {
 	case CPLD_SELECT_BANK0:
-		altbank = CPLD_SELECT_BANK4;
-		CPLD_WRITE(vbank, altbank);
-		override = CPLD_READ(software_on);
-		CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN);
-		CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET);
-		break;
 	case CPLD_SELECT_BANK4:
-		altbank = CPLD_SELECT_BANK0;
+		altbank = CPLD_SELECT_BANK4;
 		CPLD_WRITE(vbank, altbank);
 		override = CPLD_READ(software_on);
 		CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN);