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| author | Adrian Alonso <adrian.alonso@nxp.com> | 2016-08-25 13:28:34 -0500 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2017-04-05 14:07:05 +0800 |
| commit | 62d2c94a9bf0c8ef6a9d5c712af78cb0056fc54d (patch) | |
| tree | 6a15097a6750a74d3af71a75de7ccb6fe22bd058 /board/freescale | |
| parent | c386d74718c1dd9389928a6e8ff37b5c826ae2b2 (diff) | |
| download | u-boot-imx-62d2c94a9bf0c8ef6a9d5c712af78cb0056fc54d.zip u-boot-imx-62d2c94a9bf0c8ef6a9d5c712af78cb0056fc54d.tar.gz u-boot-imx-62d2c94a9bf0c8ef6a9d5c712af78cb0056fc54d.tar.bz2 | |
MLK-13132: mx6qarm2: mt128x64mx32: adjust ahb/axi podf dividers
Adjust ahb/axi clock root podf dividers to be divided by 1
to allow ahb/axi clock root to be 24Mhz when sourced
from osc_clk.
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
(cherry picked from commit 9e80234c823d6a2a0d9e10ab4c4c605bf646bd22)
Diffstat (limited to 'board/freescale')
| -rw-r--r-- | board/freescale/mx6qarm2/mt128x64mx32.cfg | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/freescale/mx6qarm2/mt128x64mx32.cfg b/board/freescale/mx6qarm2/mt128x64mx32.cfg index babd2d1..4d66416 100644 --- a/board/freescale/mx6qarm2/mt128x64mx32.cfg +++ b/board/freescale/mx6qarm2/mt128x64mx32.cfg @@ -44,7 +44,7 @@ CSF CONFIG_CSF_SIZE #ifdef CONFIG_MX6DQ_POP_LPDDR2 /* set ddr to 400Mhz */ DATA 4 0x020C4018 0x21324 -DATA 4 0x020C4014 0x2018900 +DATA 4 0x020C4014 0x2018100 CHECK_BITS_CLR 4 0x020C4048 0x3F DATA 4 0x020C4018 0x61324 DATA 4 0x020C4014 0x18900 |