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| author | York Sun <yorksun@freescale.com> | 2013-06-25 11:37:45 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-08-09 12:41:39 -0700 |
| commit | d8556db1d4d97b03b7868cae12800ecee877c8b4 (patch) | |
| tree | 2a557d4b97d84b01ef3aa3100249bad2d208d8b4 /board/freescale/t4qds/ddr.h | |
| parent | 1cb19fbb31dc7fd2c3a15667c60c6296d392f96c (diff) | |
| download | u-boot-imx-d8556db1d4d97b03b7868cae12800ecee877c8b4.zip u-boot-imx-d8556db1d4d97b03b7868cae12800ecee877c8b4.tar.gz u-boot-imx-d8556db1d4d97b03b7868cae12800ecee877c8b4.tar.bz2 | |
powerpc/mpc8xxx: Set inactive csn_bnds to 0xffffffff
When chip select interleaving is enabled, cs0_bnds is used for address
binding. Other csn_bnds are not used. When two controllers interleaving is
enabled, cs0_bnds of both controllers are used, other csn_bnds are not.
However, the unused csn_bnds may be used internally for calculating
addresses for calibration. Setting those registers to 0 may confuse
controllers in some cases. Instead, setting them to 0xffffffff together
with normal LAWs will guarantee the address is not mapped to DDR.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/t4qds/ddr.h')
0 files changed, 0 insertions, 0 deletions