diff options
| author | Shengzhou Liu <Shengzhou.Liu@freescale.com> | 2014-04-18 16:43:41 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-04-22 17:58:52 -0700 |
| commit | ef531c73570794b7676b62de4224bd294919b83b (patch) | |
| tree | bb21d9aed665fd694d1f6bac988fc68fa7f86c4a /board/freescale/t208xrdb/README | |
| parent | 4d66668300439972abc4990f23fdea771f0830fd (diff) | |
| download | u-boot-imx-ef531c73570794b7676b62de4224bd294919b83b.zip u-boot-imx-ef531c73570794b7676b62de4224bd294919b83b.tar.gz u-boot-imx-ef531c73570794b7676b62de4224bd294919b83b.tar.bz2 | |
board/t2080rdb: some update for t2080rdb
- update readme.
- add CONFIG_SYS_CORTINA_FW_IN_* for loading Cortina PHY CS4315
ucode from NOR/NAND/SPI/SD/REMOTE.
- update cpld vbank with SW3[5:7]=000 as default vbank0 instead of
previous SW3[5:7]=111 as default vbank.
- fix CONFIG_SYS_I2C_EEPROM_ADDR_LEN to 2.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/t208xrdb/README')
| -rw-r--r-- | board/freescale/t208xrdb/README | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/board/freescale/t208xrdb/README b/board/freescale/t208xrdb/README index fe26de5..24484cd 100644 --- a/board/freescale/t208xrdb/README +++ b/board/freescale/t208xrdb/README @@ -67,7 +67,7 @@ T2080PCIe-RDB board Overview - One PCIe x2 end-point device (C293 Crypto co-processor) - IFC/Local Bus - NOR: 128MB 16-bit NOR Flash - - NAND: 512MB 8-bit NAND flash + - NAND: 1GB 8-bit NAND flash - CPLD: for system controlling with programable header on-board - SATA - Two SATA 2.0 onnectors on-board @@ -156,11 +156,11 @@ Software configurations and board settings Switching between default bank and alternate bank on NOR flash To change boot source to vbank4: via software: run command 'cpld reset altbank' in u-boot. - via DIP-switch: set SW3[5:7] = '011' + via DIP-switch: set SW3[5:7] = '100' To change boot source to vbank0: via software: run command 'cpld reset' in u-boot. - via DIP-Switch: set SW3[5:7] = '111' + via DIP-Switch: set SW3[5:7] = '000' 2. NAND Boot: a. build PBL image for NAND boot |