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| author | Alison Wang <b18965@freescale.com> | 2014-10-17 15:26:36 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-11-24 09:27:24 -0800 |
| commit | 0ab172353e14dbdb7278755de6feae3fc4b54c2f (patch) | |
| tree | 2e18ee3aec0b22ec380428433878a5ccde771785 /board/freescale/p2020come | |
| parent | 5175a2885fbb47e4836dcb8ad0ad2214e9b0b3b5 (diff) | |
| download | u-boot-imx-0ab172353e14dbdb7278755de6feae3fc4b54c2f.zip u-boot-imx-0ab172353e14dbdb7278755de6feae3fc4b54c2f.tar.gz u-boot-imx-0ab172353e14dbdb7278755de6feae3fc4b54c2f.tar.bz2 | |
arm: ls102xa: Select ge2_clk125 for eTSEC clock muxing
EC1 pins in RCW can be selected as RGMII1, GPIO3, CAN1/2, FTM1 or
SAI1/2. There is a bug that EC3 RGMII could not work when selecting EC1
as other functionality except RGMII. The workaround is to select
ge2_clk125 for eTSEC clock muxing in register SCFG_ETSECCMCR.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/p2020come')
0 files changed, 0 insertions, 0 deletions