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authorKumar Gala <galak@kernel.crashing.org>2009-09-03 10:09:04 -0500
committerKumar Gala <galak@kernel.crashing.org>2009-09-24 12:04:58 -0500
commit93a83872c707891bad22f7776d79a650c870601f (patch)
tree7e14ea2c46fded75f36bd13266290fb35f491b39 /board/freescale/p1_p2_rdb
parent62ca21c442e18fec118ec83e183d64ea49966ce7 (diff)
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ppc/85xx: Clean up p1_p2_rdb PCI setup
General code cleanup to use in/out IO accessors as well as making the code that prints out info sane between board and generic fsl pci code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/freescale/p1_p2_rdb')
-rw-r--r--board/freescale/p1_p2_rdb/pci.c42
1 files changed, 22 insertions, 20 deletions
diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c
index a3617d5..4c08f9e 100644
--- a/board/freescale/p1_p2_rdb/pci.c
+++ b/board/freescale/p1_p2_rdb/pci.c
@@ -41,60 +41,62 @@ static struct pci_controller pcie2_hose;
void pci_init_board(void)
{
- struct fsl_pci_info pci_info[2];
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- uint devdisr = in_be32(&gur->devdisr);
- uint io_sel = (in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- uint host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16;
- int num = 0;
+ struct fsl_pci_info pci_info[2];
+ u32 devdisr, pordevsr, io_sel, host_agent;
int first_free_busno = 0;
+ int num = 0;
int pcie_ep, pcie_configured;
+ devdisr = in_be32(&gur->devdisr);
+ pordevsr = in_be32(&gur->pordevsr);
+ io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+ host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16;
+
debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
devdisr, io_sel, host_agent);
- if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
+ if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
printf (" eTSEC2 is in sgmii mode.\n");
+ puts("\n");
#ifdef CONFIG_PCIE2
- SET_STD_PCIE_INFO(pci_info[num], 2);
pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
- puts ("\n PCIE2 connected to Slot 1 as ");
- printf ("%s (base address %lx)",
- pcie_ep ? "End Point": "Root Complex", pci_info[num].regs);
- first_free_busno = fsl_pci_init_port(&pci_info[num],
+ SET_STD_PCIE_INFO(pci_info[num], 2);
+ printf(" PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
+ pcie_ep ? "End Point" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie2_hose, first_free_busno);
- num++;
} else {
printf (" PCIE2: disabled\n");
}
+ puts("\n");
#else
- set_bits32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
#endif
#ifdef CONFIG_PCIE1
- SET_STD_PCIE_INFO(pci_info[num], 1);
-
pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
- puts ("\n PCIE1 connected to Slot 2 as ");
- printf ("%s (base address %lx)",
+ SET_STD_PCIE_INFO(pci_info[num], 1);
+ printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
- first_free_busno = fsl_pci_init_port(&pci_info[num],
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);
- num++;
} else {
printf (" PCIE1: disabled\n");
}
+ puts("\n");
#else
- set_bits32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
#endif
}