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| author | Matthew McClintock <msm@freescale.com> | 2012-05-18 06:04:17 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-08-08 17:13:37 -0500 |
| commit | af2536088e2feae2cf1274f48376e3310e0f709e (patch) | |
| tree | 50111b432dd0abc06c960b91991c38a1e6ce419c /board/freescale/p1022ds/tlb.c | |
| parent | 56249fea3d5e32cddcd9160e51ec93a9c4327c6b (diff) | |
| download | u-boot-imx-af2536088e2feae2cf1274f48376e3310e0f709e.zip u-boot-imx-af2536088e2feae2cf1274f48376e3310e0f709e.tar.gz u-boot-imx-af2536088e2feae2cf1274f48376e3310e0f709e.tar.bz2 | |
powerpc/p1022ds: add support for SPI and SD boot
Add TLB mappings, board target options, and configuration items
need for SPI/SD boot.
Since P1022DS RevB board, the NOR flash have been changed to 16 bit/28bit
address flash, therefore, when SDHC/ESPI booting and access to eLBC,
the PMUXCR[0~1] must be set to 10b, and PMUXCR[9~10] must be set to
00b for them.
Configure the PX_BRDCFG0[0~1] to 10b which is connected to
SPI devices as SPI_CS(0:3)_B.
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/freescale/p1022ds/tlb.c')
| -rw-r--r-- | board/freescale/p1022ds/tlb.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/board/freescale/p1022ds/tlb.c b/board/freescale/p1022ds/tlb.c index e620112..71e71f7 100644 --- a/board/freescale/p1022ds/tlb.c +++ b/board/freescale/p1022ds/tlb.c @@ -71,6 +71,20 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_4K, 1), + +#ifdef CONFIG_SYS_RAMBOOT + /* *I*G - eSDHC/eSPI/NAND boot */ + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 8, BOOKE_PAGESZ_1G, 1), + + /* map the second 1G */ + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 9, BOOKE_PAGESZ_1G, 1), +#endif +# }; int num_tlb_entries = ARRAY_SIZE(tlb_table); |