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author | Anson Huang <Anson.Huang@nxp.com> | 2016-04-26 17:46:33 +0800 |
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committer | Frank Li <Frank.Li@nxp.com> | 2016-04-29 10:08:53 -0500 |
commit | b47c715c5e5afb1f0468bf3052cc02203f91ad6a (patch) | |
tree | 885ca82861a7ffbd4527bed5f19d27a0698fe9bb /board/freescale/mx7dsabresd/imximage_TO_1_1.cfg | |
parent | d7d7c4312b71dd3879fa8640b23f6a5bac30e303 (diff) | |
download | u-boot-imx-b47c715c5e5afb1f0468bf3052cc02203f91ad6a.zip u-boot-imx-b47c715c5e5afb1f0468bf3052cc02203f91ad6a.tar.gz u-boot-imx-b47c715c5e5afb1f0468bf3052cc02203f91ad6a.tar.bz2 |
MLK-12705-1 ARM: imx: add support for i.MX7D TO1.2
i.MX7D TO1.2 uses same DDR script as TO1.0,
TO1.1 uses dedicated DDR script.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'board/freescale/mx7dsabresd/imximage_TO_1_1.cfg')
-rw-r--r-- | board/freescale/mx7dsabresd/imximage_TO_1_1.cfg | 124 |
1 files changed, 124 insertions, 0 deletions
diff --git a/board/freescale/mx7dsabresd/imximage_TO_1_1.cfg b/board/freescale/mx7dsabresd/imximage_TO_1_1.cfg new file mode 100644 index 0000000..db4c939 --- /dev/null +++ b/board/freescale/mx7dsabresd/imximage_TO_1_1.cfg @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include <config.h> + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_SYS_BOOT_QSPI +BOOT_FROM qspi +#elif defined(CONFIG_SYS_BOOT_EIMNOR) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7dsabresd/plugin.bin 0x00910000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x30360070 0x00703021 +DATA 4 0x30360090 0x0 +DATA 4 0x30360070 0x00603021 +CHECK_BITS_SET 4 0x30360070 0x80000000 +DATA 4 0x30389880 0x1 + +DATA 4 0x30340004 0x4F400005 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x01040001 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 +DATA 4 0x307a0064 0x00400046 +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00020083 +DATA 4 0x307a00d4 0x00690000 +DATA 4 0x307a00dc 0x09300004 +DATA 4 0x307a00e0 0x04080000 +DATA 4 0x307a00e4 0x00100004 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x09081109 +DATA 4 0x307a0104 0x0007020d +DATA 4 0x307a0108 0x03040407 +DATA 4 0x307a010c 0x00002006 +DATA 4 0x307a0110 0x04020205 +DATA 4 0x307a0114 0x03030202 +DATA 4 0x307a0120 0x00000803 +DATA 4 0x307a0180 0x00800020 +DATA 4 0x307a0184 0x02000100 +DATA 4 0x307a0190 0x02098204 +DATA 4 0x307a0194 0x00030303 +DATA 4 0x307a0200 0x00000016 +DATA 4 0x307a0204 0x00171717 +DATA 4 0x307a0214 0x04040404 +DATA 4 0x307a0218 0x0f040404 +DATA 4 0x307a0240 0x06000604 +DATA 4 0x307a0244 0x00000001 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17420f40 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790010 0x00060807 +DATA 4 0x307900b0 0x1010007e +DATA 4 0x3079009c 0x00000dee +DATA 4 0x3079007c 0x18181818 +DATA 4 0x30790080 0x18181818 +DATA 4 0x30790084 0x40401818 +DATA 4 0x30790088 0x00000040 +DATA 4 0x3079006c 0x40404040 +DATA 4 0x30790020 0x08080808 +DATA 4 0x30790030 0x08080808 +DATA 4 0x30790050 0x01000010 +DATA 4 0x30790050 0x00000010 + +DATA 4 0x307900c0 0x0e407304 +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e447306 + +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e407304 + + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x00000178 +DATA 4 0x30384130 0x00000002 +DATA 4 0x30790018 0x0000000f + +CHECK_BITS_SET 4 0x307a0004 0x1 + +#endif |