diff options
| author | Ye Li <ye.li@nxp.com> | 2016-12-01 13:39:41 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2017-04-05 19:48:57 +0800 |
| commit | d78d25cfb4cf64507e5839e525ce82e0897a609c (patch) | |
| tree | b28a3e5b2c1ebf22c3ee0b1a14bc864efc18d09f /board/freescale/mx7d_19x19_lpddr3_arm2/plugin.S | |
| parent | dc2318b60ba7be0b313580e0e8f6556d09a962fa (diff) | |
| download | u-boot-imx-d78d25cfb4cf64507e5839e525ce82e0897a609c.zip u-boot-imx-d78d25cfb4cf64507e5839e525ce82e0897a609c.tar.gz u-boot-imx-d78d25cfb4cf64507e5839e525ce82e0897a609c.tar.bz2 | |
MLK-13586-1 mx7d_arm2: Update lpddr3 script to V2.0 for Bank interleave
To improve the performance, enable the bank interleave for LPDDR3. Update
the LPDDR3 settings to new script IMX7D_LPDDR3_533MHz_2GB_32bit_V2.0.ds5.
Changes:
1. Enable bank interleave
2. Improve the drive strength for non-TO1.1 chips.
3. Updates ZQ_CON0 settings.
4. Change to 0 for reserved bits.
File:
http://compass.freescale.net/livelink/livelink?func=ll&objid=233861153&objAction=browse&sort=name&viewType=1
Test:
Passed stress test on one 19x19 lpddr3 arm2 and one 12x12 lpddr3 arm2.
Passed LPSR test on one 12x12 lpddr3 arm2.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 9a4fa3f8d2762791a76fd90e83feec8c8c9235b0)
Diffstat (limited to 'board/freescale/mx7d_19x19_lpddr3_arm2/plugin.S')
| -rw-r--r-- | board/freescale/mx7d_19x19_lpddr3_arm2/plugin.S | 31 |
1 files changed, 20 insertions, 11 deletions
diff --git a/board/freescale/mx7d_19x19_lpddr3_arm2/plugin.S b/board/freescale/mx7d_19x19_lpddr3_arm2/plugin.S index 319237a..85db174 100644 --- a/board/freescale/mx7d_19x19_lpddr3_arm2/plugin.S +++ b/board/freescale/mx7d_19x19_lpddr3_arm2/plugin.S @@ -122,16 +122,16 @@ TUNE_END: ldr r1, =0x00000016 str r1, [r0, #0x200] - ldr r1, =0x00171717 + ldr r1, =0x00090909 str r1, [r0, #0x204] ldr r1, =0x00000f00 str r1, [r0, #0x210] - ldr r1, =0x05050505 + ldr r1, =0x08080808 str r1, [r0, #0x214] - ldr r1, =0x0f0f0505 + ldr r1, =0x0f0f0808 str r1, [r0, #0x218] - ldr r1, =0x06000601 + ldr r1, =0x06000600 str r1, [r0, #0x240] mov r1, #0x0 str r1, [r0, #0x244] @@ -155,9 +155,20 @@ TUNE_END: str r1, [r0, #0xb0] ldr r1, =0x01010000 str r1, [r0, #0x1c] + + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne 1f + ldr r1, =0x0db60d6e str r1, [r0, #0x9c] - + b 2f +1: + ldr r1, =0x00000b24 + str r1, [r0, #0x9c] +2: ldr r1, =0x06060606 str r1, [r0, #0x30] ldr r1, =0x0a0a0a0a @@ -169,13 +180,11 @@ TUNE_END: ldr r1, =0x0000000f str r1, [r0, #0x18] - ldr r1, =0x1e487304 - str r1, [r0, #0xc0] - ldr r1, =0x1e487304 + ldr r1, =0x0e487304 str r1, [r0, #0xc0] - ldr r1, =0x1e487306 + ldr r1, =0x0e4c7304 str r1, [r0, #0xc0] - ldr r1, =0x1e4c7304 + ldr r1, =0x0e4c7306 str r1, [r0, #0xc0] wait_zq: @@ -183,7 +192,7 @@ wait_zq: tst r1, #0x1 beq wait_zq - ldr r1, =0x1e487304 + ldr r1, =0x0e487304 str r1, [r0, #0xc0] ldr r0, =CCM_BASE_ADDR |