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author | Peng Fan <peng.fan@nxp.com> | 2017-02-08 15:51:59 +0800 |
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committer | Ye Li <ye.li@nxp.com> | 2017-04-05 17:23:50 +0800 |
commit | 9c0c98c0db3c2189c09f6b8e28b3f2d3fade6c11 (patch) | |
tree | c4e08097c154b3fad39fb9d9ff4387b0f6b3a53a /board/freescale/mx7d_19x19_lpddr3_arm2/imximage_lpddr2.cfg | |
parent | db7d3954b773a2b67e4211606551c06c7573df10 (diff) | |
download | u-boot-imx-9c0c98c0db3c2189c09f6b8e28b3f2d3fade6c11.zip u-boot-imx-9c0c98c0db3c2189c09f6b8e28b3f2d3fade6c11.tar.gz u-boot-imx-9c0c98c0db3c2189c09f6b8e28b3f2d3fade6c11.tar.bz2 |
MLK-14419-3 imx: mx7d_arm2: add 19x19 LPDDR2/LPDDR3/DDR3 ARM2 support
Add 19x19 LPDDR2/LPDDR3/DDR3 ARM2 board supports.
Enable the OF_CONTROL and convert them to use DM driver. Since the DTB lacks
the support for some modules. We have to use QSPI and FEC with non-DM driver.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'board/freescale/mx7d_19x19_lpddr3_arm2/imximage_lpddr2.cfg')
-rw-r--r-- | board/freescale/mx7d_19x19_lpddr3_arm2/imximage_lpddr2.cfg | 119 |
1 files changed, 119 insertions, 0 deletions
diff --git a/board/freescale/mx7d_19x19_lpddr3_arm2/imximage_lpddr2.cfg b/board/freescale/mx7d_19x19_lpddr3_arm2/imximage_lpddr2.cfg new file mode 100644 index 0000000..171d2ad --- /dev/null +++ b/board/freescale/mx7d_19x19_lpddr3_arm2/imximage_lpddr2.cfg @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include <config.h> + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_SYS_BOOT_QSPI +BOOT_FROM qspi +#elif defined(CONFIG_SYS_BOOT_EIMNOR) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7d_19x19_lpddr3_arm2/plugin.bin 0x00910000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x30340004 0x4F400005 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x03020004 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 +DATA 4 0x307a0064 0x00200023 +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00350001 +DATA 4 0x307a00d8 0x00001105 +DATA 4 0x307a00dc 0x00c20006 +DATA 4 0x307a00e0 0x00020000 +DATA 4 0x307a00e4 0x00110006 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x080e110b +DATA 4 0x307a0104 0x00020211 +DATA 4 0x307a0108 0x02040706 +DATA 4 0x307a010c 0x00504000 +DATA 4 0x307a0110 0x05010307 +DATA 4 0x307a0114 0x02020404 +DATA 4 0x307a0118 0x02020003 +DATA 4 0x307a011c 0x00000202 +DATA 4 0x307a0120 0x00000202 + +DATA 4 0x307a0180 0x00600018 +DATA 4 0x307a0184 0x00e00100 +DATA 4 0x307a0190 0x02098203 +DATA 4 0x307a0194 0x00060303 + +DATA 4 0x307a0200 0x00000015 +DATA 4 0x307a0204 0x00161616 +DATA 4 0x307a0210 0x00000f0f +DATA 4 0x307a0214 0x04040404 +DATA 4 0x307a0218 0x0f0f0404 + +DATA 4 0x307a0240 0x06000600 +DATA 4 0x307a0244 0x00000000 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17421640 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790008 0x00010000 +DATA 4 0x30790010 0x00050408 +DATA 4 0x307900b0 0x1010007e + +DATA 4 0x3079001C 0x01010000 +DATA 4 0x3079009C 0x00000d6e +DATA 4 0x30790018 0x0000000f + +DATA 4 0x30790030 0x06060606 +DATA 4 0x30790020 0x0a0a0a0a +DATA 4 0x30790050 0x01000008 +DATA 4 0x30790050 0x00000008 +DATA 4 0x307900c0 0x0e487304 +DATA 4 0x307900c0 0x0e4c7304 +DATA 4 0x307900c0 0x0e4c7306 +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x0e4c7304 +DATA 4 0x307900c0 0x0e487304 + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x000001f8 +DATA 4 0x30384130 0x00000002 + +CHECK_BITS_SET 4 0x307a0004 0x1 +#endif |