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| author | Ye Li <ye.li@nxp.com> | 2016-07-28 11:42:14 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2016-07-29 10:11:25 +0800 |
| commit | fd8fbf7fa0b10199ac89cd13cae851149f51accb (patch) | |
| tree | db4a9d85a98124d30de3c8d28f91fe5c82db4e26 /board/freescale/mx6ull_ddr3_arm2 | |
| parent | 81f74e47fccd4845e265030ff50c1bc6b9ee18dd (diff) | |
| download | u-boot-imx-fd8fbf7fa0b10199ac89cd13cae851149f51accb.zip u-boot-imx-fd8fbf7fa0b10199ac89cd13cae851149f51accb.tar.gz u-boot-imx-fd8fbf7fa0b10199ac89cd13cae851149f51accb.tar.bz2 | |
MLK-12996 imx: mx6dqp/dq: Fix SATA read/write fail after booting from SATA
We found a issue in PLL6 ENET that changing the bit[1:0] DIV_SELECT for ENET
ref clock will impact the SATA ref 100Mhz clock. If SATA is initialized before
this changing, SATA read/write can't work after it. And we have to re-init SATA.
The issue can reproduce on both i.MX6DQP and i.MX6DQ. IC investigation is ongoing.
This patch is an work around that moves the ENET clock setting
(enable_fec_anatop_clock) from ethernet init to board_init which is prior
than SATA initialization. So there is no PLL6 change after SATA init.
Signed-off-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'board/freescale/mx6ull_ddr3_arm2')
0 files changed, 0 insertions, 0 deletions