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authorYe Li <ye.li@nxp.com>2016-04-19 09:54:51 +0800
committerYe Li <ye.li@nxp.com>2016-04-20 14:35:17 +0800
commit5c8c027bcd9be6a45511f58e6b9f1a5ed1516d4a (patch)
treefd8254b34ca9522fa7353227dd076a9f2f32b9d2 /board/freescale/mx6ull_ddr3_arm2
parentc5f3ebc2b4a3d01f2a923776450661787dd0aee3 (diff)
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MLK-12677 mx6ullarm2: Update DDR script to version 2.1
File: IMX6ULL_DDR3L_400MHz_1GB_16bit_V2.1.inc Changes: Change ZQ_OFFSET to the default value:00 setmem /32 0x021B0890 = 0x00400000 Change IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET.DDR_SEL to 11 setmem /32 0x020E0288 = 0x000C0030 Change duty cycle fine tune cell for SDCLK and SDQS setmem /32 0x021B08C0 = 0x00944009 Test: One mx6ull ARM2 board passed memtest. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 8128b2f3b419a1d15a0489a91e56a4ac82eaf0c4)
Diffstat (limited to 'board/freescale/mx6ull_ddr3_arm2')
-rw-r--r--board/freescale/mx6ull_ddr3_arm2/imximage.cfg6
-rw-r--r--board/freescale/mx6ull_ddr3_arm2/plugin.S5
2 files changed, 6 insertions, 5 deletions
diff --git a/board/freescale/mx6ull_ddr3_arm2/imximage.cfg b/board/freescale/mx6ull_ddr3_arm2/imximage.cfg
index 55a4a44..0fc39f7 100644
--- a/board/freescale/mx6ull_ddr3_arm2/imximage.cfg
+++ b/board/freescale/mx6ull_ddr3_arm2/imximage.cfg
@@ -64,7 +64,7 @@ DATA 4 0x020E027C 0x00000030
DATA 4 0x020E0250 0x00000030
DATA 4 0x020E024C 0x00000030
DATA 4 0x020E0490 0x00000030
-DATA 4 0x020E0288 0x00000030
+DATA 4 0x020E0288 0x000C0030
DATA 4 0x020E0270 0x00000000
DATA 4 0x020E0260 0x00000030
DATA 4 0x020E0264 0x00000030
@@ -87,7 +87,7 @@ DATA 4 0x021B081C 0x33333333
DATA 4 0x021B0820 0x33333333
DATA 4 0x021B082C 0xf3333333
DATA 4 0x021B0830 0xf3333333
-DATA 4 0x021B08C0 0x00921012
+DATA 4 0x021B08C0 0x00944009
DATA 4 0x021B08b8 0x00000800
DATA 4 0x021B0004 0x0002002D
DATA 4 0x021B0008 0x1B333030
@@ -100,7 +100,7 @@ DATA 4 0x021B002C 0x000026D2
DATA 4 0x021B0030 0x006B1023
DATA 4 0x021B0040 0x0000005F
DATA 4 0x021B0000 0x85180000
-DATA 4 0x021B0890 0x00400A38
+DATA 4 0x021B0890 0x00400000
DATA 4 0x021B001C 0x02008032
DATA 4 0x021B001C 0x00008033
DATA 4 0x021B001C 0x00048031
diff --git a/board/freescale/mx6ull_ddr3_arm2/plugin.S b/board/freescale/mx6ull_ddr3_arm2/plugin.S
index 9cf484c..e32cc13 100644
--- a/board/freescale/mx6ull_ddr3_arm2/plugin.S
+++ b/board/freescale/mx6ull_ddr3_arm2/plugin.S
@@ -18,6 +18,7 @@
str r1, [r0, #0x250]
str r1, [r0, #0x24C]
str r1, [r0, #0x490]
+ ldr r1, =0x000C0030
str r1, [r0, #0x288]
ldr r1, =0x00000000
@@ -63,7 +64,7 @@
ldr r1, =0xF3333333
str r1, [r0, #0x82C]
str r1, [r0, #0x830]
- ldr r1, =0x00922012
+ ldr r1, =0x00944009
str r1, [r0, #0x8C0]
ldr r1, =0x00000800
str r1, [r0, #0x8B8]
@@ -89,7 +90,7 @@
str r1, [r0, #0x040]
ldr r1, =0x85180000
str r1, [r0, #0x000]
- ldr r1, =0x00400A38
+ ldr r1, =0x00400000
str r1, [r0, #0x890]
ldr r1, =0x02008032
str r1, [r0, #0x01C]