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| author | Robin Gong <b38343@freescale.com> | 2012-11-16 15:25:49 +0800 |
|---|---|---|
| committer | Robin Gong <b38343@freescale.com> | 2012-11-19 10:45:13 +0800 |
| commit | 95c7393cf3836314c9b26dcc29ea3a75b4d5f8b2 (patch) | |
| tree | 36688fdfd150a420cb197c003a569030635d1c8f /board/freescale/mx6sl_arm2 | |
| parent | bbbdf5aa5605f7817e8561506e59a7c3f39e6402 (diff) | |
| download | u-boot-imx-95c7393cf3836314c9b26dcc29ea3a75b4d5f8b2.zip u-boot-imx-95c7393cf3836314c9b26dcc29ea3a75b4d5f8b2.tar.gz u-boot-imx-95c7393cf3836314c9b26dcc29ea3a75b4d5f8b2.tar.bz2 | |
ENGR00233366-5 Anatop PFUZE: move LDO bypass code to kernel
move LDO bypass code and one PFUZE1.0 workaround code to kernel. Remove
CONFIG_MX6_INTER_LDO_BYPASS in u-boot
Signed-off-by: Robin Gong <b38343@freescale.com>
Diffstat (limited to 'board/freescale/mx6sl_arm2')
| -rw-r--r-- | board/freescale/mx6sl_arm2/mx6sl_arm2.c | 39 |
1 files changed, 0 insertions, 39 deletions
diff --git a/board/freescale/mx6sl_arm2/mx6sl_arm2.c b/board/freescale/mx6sl_arm2/mx6sl_arm2.c index f695066..ad6f47f 100644 --- a/board/freescale/mx6sl_arm2/mx6sl_arm2.c +++ b/board/freescale/mx6sl_arm2/mx6sl_arm2.c @@ -952,9 +952,6 @@ int i2c_bus_recovery(void) static int setup_pmic_voltages(void) { unsigned char value, rev_id = 0 ; - #if CONFIG_MX6_INTER_LDO_BYPASS - unsigned int val = 0; - #endif i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); if (!i2c_probe(0x8)) { if (i2c_read(0x8, 0, 1, &value, 1)) { @@ -966,42 +963,6 @@ static int setup_pmic_voltages(void) return -1; } printf("Found PFUZE100! deviceid=%x,revid=%x\n", value, rev_id); - #if CONFIG_MX6_INTER_LDO_BYPASS - /*VDDCORE 1.1V@800Mhz: SW1AB*/ - value = 0x20; - if (i2c_write(0x8, 0x20, 1, &value, 1)) { - printf("VDDCORE set voltage error!\n"); - return -1; - } - - /*VDDSOC 1.2V : SW1C*/ - value = 0x24; - if (i2c_write(0x8, 0x2e, 1, &value, 1)) { - printf("VDDSOC set voltage error!\n"); - return -1; - } - - /* Bypass the VDDSOC from Anatop */ - val = REG_RD(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE); - val &= ~BM_ANADIG_REG_CORE_REG2_TRG; - val |= BF_ANADIG_REG_CORE_REG2_TRG(0x1f); - REG_WR(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE, val); - - /* Bypass the VDDCORE from Anatop */ - val = REG_RD(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE); - val &= ~BM_ANADIG_REG_CORE_REG0_TRG; - val |= BF_ANADIG_REG_CORE_REG0_TRG(0x1f); - REG_WR(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE, val); - - /* Bypass the VDDPU from Anatop */ - val = REG_RD(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE); - val &= ~BM_ANADIG_REG_CORE_REG1_TRG; - val |= BF_ANADIG_REG_CORE_REG1_TRG(0x1f); - REG_WR(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE, val); - - printf("hw_anadig_reg_core=%x\n", - REG_RD(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE)); - #endif } } |