ENGR00315894-1 iMX6q/dl:SABREAUTO/SABRESD: Refactor configurations for more iMX6 boards

1. Make the DDR size configurable based on the boards.cfg
2. Make the FDT file configurable based on the boards.cfg
3. Add DDR and boot configuration script for iMX6dl.
   Change default boot from SD card.
   The DDR script has been updated to the v1.5 version from ddr-scripts-rel
   commit: bfd157a Updated MX6DL and MX6DQ ARD and SabreSD scripts.

Signed-off-by: Ye.Li <B37916@freescale.com>

2 files changed, 155 insertions, 1 deletions

diff --git a/board/freescale/mx6sabresd/mx6dl_4x_mt41j128.cfg b/board/freescale/mx6sabresd/mx6dl_4x_mt41j128.cfg
new file mode 100644
index 0000000..a2b7e48
--- /dev/null
+++ b/board/freescale/mx6sabresd/mx6dl_4x_mt41j128.cfg
@@ -0,0 +1,154 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of spi, sd, sata
+ * the board has no nand and eimnor
+ * spinor: flash_offset: 0x0400
+ * sata:   flash_offset: 0x0400
+ * sd/mmc: flash_offset: 0x0400
+ */
+
+/* the same flash_offset as sd */
+BOOT_FROM      sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+DATA 4,	0x020e0774, 0x000C0000
+DATA 4,	0x020e0754, 0x00000000
+DATA 4,	0x020e04ac, 0x00000030
+DATA 4,	0x020e04b0, 0x00000030
+DATA 4,	0x020e0464, 0x00000030
+DATA 4,	0x020e0490, 0x00000030
+DATA 4,	0x020e074c, 0x00000030
+DATA 4,	0x020e0494, 0x00000030
+DATA 4,	0x020e04a0, 0x00000000
+DATA 4,	0x020e04b4, 0x00000030
+DATA 4,	0x020e04b8, 0x00000030
+DATA 4,	0x020e076c, 0x00000030
+DATA 4,	0x020e0750, 0x00020000
+DATA 4,	0x020e04bc, 0x00000030
+DATA 4,	0x020e04c0, 0x00000030
+DATA 4,	0x020e04c4, 0x00000030
+DATA 4,	0x020e04c8, 0x00000030
+DATA 4,	0x020e04cc, 0x00000030
+DATA 4,	0x020e04d0, 0x00000030
+DATA 4,	0x020e04d4, 0x00000030
+DATA 4,	0x020e04d8, 0x00000030
+DATA 4,	0x020e0760, 0x00020000
+DATA 4,	0x020e0764, 0x00000030
+DATA 4,	0x020e0770, 0x00000030
+DATA 4,	0x020e0778, 0x00000030
+DATA 4,	0x020e077c, 0x00000030
+DATA 4,	0x020e0780, 0x00000030
+DATA 4,	0x020e0784, 0x00000030
+DATA 4,	0x020e078c, 0x00000030
+DATA 4,	0x020e0748, 0x00000030
+DATA 4,	0x020e0470, 0x00000030
+DATA 4,	0x020e0474, 0x00000030
+DATA 4,	0x020e0478, 0x00000030
+DATA 4,	0x020e047c, 0x00000030
+DATA 4,	0x020e0480, 0x00000030
+DATA 4,	0x020e0484, 0x00000030
+DATA 4,	0x020e0488, 0x00000030
+DATA 4,	0x020e048c, 0x00000030
+DATA 4,	0x021b0800, 0xa1390003
+DATA 4,	0x021b080c, 0x001F001F
+DATA 4,	0x021b0810, 0x001F001F
+DATA 4,	0x021b480c, 0x001F001F
+DATA 4,	0x021b4810, 0x001F001F
+DATA 4,	0x021b083c, 0x4220021F
+DATA 4,	0x021b0840, 0x0207017E
+DATA 4,	0x021b483c, 0x4201020C
+DATA 4,	0x021b4840, 0x01660172
+DATA 4,	0x021b0848, 0x4A4D4E4D
+DATA 4,	0x021b4848, 0x4A4F5049
+DATA 4,	0x021b0850, 0x3F3C3D31
+DATA 4,	0x021b4850, 0x3238372B
+DATA 4,	0x021b081c, 0x33333333
+DATA 4,	0x021b0820, 0x33333333
+DATA 4,	0x021b0824, 0x33333333
+DATA 4,	0x021b0828, 0x33333333
+DATA 4,	0x021b481c, 0x33333333
+DATA 4,	0x021b4820, 0x33333333
+DATA 4,	0x021b4824, 0x33333333
+DATA 4,	0x021b4828, 0x33333333
+DATA 4,	0x021b08b8, 0x00000800
+DATA 4,	0x021b48b8, 0x00000800
+DATA 4,	0x021b0004, 0x0002002D
+DATA 4,	0x021b0008, 0x00333030
+DATA 4,	0x021b000c, 0x3F435313
+DATA 4,	0x021b0010, 0xB66E8B63
+DATA 4,	0x021b0014, 0x01FF00DB
+DATA 4,	0x021b0018, 0x00001740
+DATA 4,	0x021b001c, 0x00008000
+DATA 4,	0x021b002c, 0x000026d2
+DATA 4,	0x021b0030, 0x00431023
+DATA 4,	0x021b0040, 0x00000027
+DATA 4,	0x021b0000, 0x831A0000
+DATA 4,	0x021b001c, 0x04008032
+DATA 4,	0x021b001c, 0x00008033
+DATA 4,	0x021b001c, 0x00048031
+DATA 4,	0x021b001c, 0x05208030
+DATA 4, 0x021b001c, 0x04008040
+DATA 4,	0x021b0020, 0x00005800
+DATA 4,	0x021b0818, 0x00011117
+DATA 4,	0x021b4818, 0x00011117
+DATA 4,	0x021b0004, 0x0002556D
+DATA 4,	0x021b0404, 0x00011006
+DATA 4,	0x021b001c, 0x00000000
+
+/* set the default clock gate to save power */
+DATA 4, 0x020c4068, 0x00C03F3F
+DATA 4, 0x020c406c, 0x0030FC03
+DATA 4, 0x020c4070, 0x0FFFC000
+DATA 4, 0x020c4074, 0x3FF00000
+DATA 4, 0x020c4078, 0x00FFF300
+DATA 4, 0x020c407c, 0x0F0000C3
+DATA 4, 0x020c4080, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, 0x020e0010, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, 0x020e0018, 0x007F007F
+DATA 4, 0x020e001c, 0x007F007F
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 82e4084..2800b57 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -83,7 +83,7 @@ struct i2c_pads_info i2c_pad_info1 = {
 
 int dram_init(void)
 {
-	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+	gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
 
 	return 0;
 }