MLK-12629-1: imx6: cache: disable L2 before touching Auxiliary Control Register

According PL310 TRM, Auxiliary Control Register
"
The register must be written to using a secure access, and it can be
read using either a secure or a NS access. If you write to this register
with a NS access, it results in a write response with a DECERR response,
and the register is not updated. Writing to this register with the L2
cache enabled, that is, bit[0] of L2 Control Register set to 1,
results in a SLVERR.
"

So If L2 cache is already enabled, chaning value of ACR will cause SLVERR,
uboot hangs.

In some cases, such as plugin, L2 Cache enabled bit is not cleared,
then "Set bit 22 in the auxiliary control register" cause uboot hangs.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

0 files changed, 0 insertions, 0 deletions