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| author | Anson Huang <b20788@freescale.com> | 2012-06-06 17:47:12 +0800 |
|---|---|---|
| committer | Anson Huang <b20788@freescale.com> | 2012-06-06 18:31:06 +0800 |
| commit | 82d93b3ceddd456892a99b6b45ceb661bb50e710 (patch) | |
| tree | dd8c8b1423f4418f2113fc2c39e609973d29d960 /board/freescale/mx6q_sabrelite/flash_header.S | |
| parent | 6f0a281d42fad88c75389869b4d1738b3c69999e (diff) | |
| download | u-boot-imx-82d93b3ceddd456892a99b6b45ceb661bb50e710.zip u-boot-imx-82d93b3ceddd456892a99b6b45ceb661bb50e710.tar.gz u-boot-imx-82d93b3ceddd456892a99b6b45ceb661bb50e710.tar.bz2 | |
ENGR00212571 [MX6]Change DRAM ODT setting to save power
We can use weak ODT setting, it will save about 50% DDR
power in runtime. Now we use 0x00007
MMDC0_MPODTCTRL MMDC1_MPODTCTRL, (Ohm)
Setting DDR_ODT imx_ODT Max_overclocking
0x22227 120 060 615MHz
0x11117 120 120 604MHz
0x00007 120 000 576MHz
0x00000 000 000 556MHz
Signed-off-by: Anson Huang <b20788@freescale.com>
Diffstat (limited to 'board/freescale/mx6q_sabrelite/flash_header.S')
| -rw-r--r-- | board/freescale/mx6q_sabrelite/flash_header.S | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/board/freescale/mx6q_sabrelite/flash_header.S b/board/freescale/mx6q_sabrelite/flash_header.S index 0fbbb86..c0ec85c 100644 --- a/board/freescale/mx6q_sabrelite/flash_header.S +++ b/board/freescale/mx6q_sabrelite/flash_header.S @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -146,8 +146,8 @@ MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x01c, 0x04008048) MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x800, 0xA1380003) MXC_DCD_ITEM(71, MMDC_P1_BASE_ADDR + 0x800, 0xA1380003) MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x020, 0x00005800) -MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x818, 0x00022227) -MXC_DCD_ITEM(74, MMDC_P1_BASE_ADDR + 0x818, 0x00022227) +MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x818, 0x00000007) +MXC_DCD_ITEM(74, MMDC_P1_BASE_ADDR + 0x818, 0x00000007) MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x83c, 0x434B0350) MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x840, 0x034C0359) |