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authorTroy Kisky <troy.kisky@boundarydevices.com>2012-03-22 12:00:31 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-04-16 14:53:58 +0200
commit148241053123f3c2388d755807438fbe44dd2139 (patch)
tree9fe038dbbe9cec28b1f9e6af030d9ee719eb2ac6 /board/freescale/mx53ard
parent607dfdf568baa506dc4ff33a38be3478820648fd (diff)
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MX53: DDR: Fix ZQHWCTRL field TZQ_CS
Currently, board files are setting this field to 0x01 which the manual says is a reserved value. Change to use the default of 0x02 - 128 cycles. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'board/freescale/mx53ard')
-rw-r--r--board/freescale/mx53ard/imximage_dd3.cfg2
1 files changed, 1 insertions, 1 deletions
diff --git a/board/freescale/mx53ard/imximage_dd3.cfg b/board/freescale/mx53ard/imximage_dd3.cfg
index 50e05af..614d29e 100644
--- a/board/freescale/mx53ard/imximage_dd3.cfg
+++ b/board/freescale/mx53ard/imximage_dd3.cfg
@@ -91,6 +91,6 @@ DATA 4 0x63fd901c 0x00028039
DATA 4 0x63fd901c 0x05208138
DATA 4 0x63fd901c 0x04008048
DATA 4 0x63fd9020 0x00005800
-DATA 4 0x63fd9040 0x04b80003
+DATA 4 0x63fd9040 0x05380003
DATA 4 0x63fd9058 0x00022227
DATA 4 0x63fd901C 0x00000000