From 148241053123f3c2388d755807438fbe44dd2139 Mon Sep 17 00:00:00 2001 From: Troy Kisky Date: Thu, 22 Mar 2012 12:00:31 +0000 Subject: MX53: DDR: Fix ZQHWCTRL field TZQ_CS Currently, board files are setting this field to 0x01 which the manual says is a reserved value. Change to use the default of 0x02 - 128 cycles. Signed-off-by: Troy Kisky Acked-by: Fabio Estevam --- board/freescale/mx53ard/imximage_dd3.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board/freescale/mx53ard') diff --git a/board/freescale/mx53ard/imximage_dd3.cfg b/board/freescale/mx53ard/imximage_dd3.cfg index 50e05af..614d29e 100644 --- a/board/freescale/mx53ard/imximage_dd3.cfg +++ b/board/freescale/mx53ard/imximage_dd3.cfg @@ -91,6 +91,6 @@ DATA 4 0x63fd901c 0x00028039 DATA 4 0x63fd901c 0x05208138 DATA 4 0x63fd901c 0x04008048 DATA 4 0x63fd9020 0x00005800 -DATA 4 0x63fd9040 0x04b80003 +DATA 4 0x63fd9040 0x05380003 DATA 4 0x63fd9058 0x00022227 DATA 4 0x63fd901C 0x00000000 -- cgit v1.1