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| author | Fred Fan <r01011@freescale.com> | 2009-11-19 16:43:08 +0800 |
|---|---|---|
| committer | Terry Lv <r65388@freescale.com> | 2009-12-04 17:14:08 +0800 |
| commit | d8667412a8b7e1ad96979bc2191b4e3fa90c8254 (patch) | |
| tree | 52f9a08604fdbb9a3dfee9e77473f7a0127126ca /board/freescale/mx35_3stack | |
| parent | 3f86cf9693f8b98c44999e81d4067943c634b421 (diff) | |
| download | u-boot-imx-d8667412a8b7e1ad96979bc2191b4e3fa90c8254.zip u-boot-imx-d8667412a8b7e1ad96979bc2191b4e3fa90c8254.tar.gz u-boot-imx-d8667412a8b7e1ad96979bc2191b4e3fa90c8254.tar.bz2 | |
ENGR00118978: Timer adjustment for all platforms
In current u-boot design,
get_timer_masked is not correct and udelay is not accurate
when the time is less than 1000us.
Thus we need to use ipg clock source for accurate timer.
Signed-off-by: Terry Lv <r65388@freescale.com>
Diffstat (limited to 'board/freescale/mx35_3stack')
| -rw-r--r-- | board/freescale/mx35_3stack/board-mx35_3stack.h | 2 | ||||
| -rw-r--r-- | board/freescale/mx35_3stack/lowlevel_init.S | 16 |
2 files changed, 9 insertions, 9 deletions
diff --git a/board/freescale/mx35_3stack/board-mx35_3stack.h b/board/freescale/mx35_3stack/board-mx35_3stack.h index f9c3074..82667ac 100644 --- a/board/freescale/mx35_3stack/board-mx35_3stack.h +++ b/board/freescale/mx35_3stack/board-mx35_3stack.h @@ -63,7 +63,7 @@ #define DBG_CSCR_A_CONFIG 0x22220A00 #define CCM_CCMR_CONFIG 0x003F4208 -#define CCM_PDR0_CONFIG 0x00821000 +#define CCM_PDR0_CONFIG 0x00801000 #define PLL_BRM_OFFSET 31 #define PLL_PD_OFFSET 26 diff --git a/board/freescale/mx35_3stack/lowlevel_init.S b/board/freescale/mx35_3stack/lowlevel_init.S index c255e98..c4454fa 100644 --- a/board/freescale/mx35_3stack/lowlevel_init.S +++ b/board/freescale/mx35_3stack/lowlevel_init.S @@ -204,9 +204,8 @@ check_soc_version r1, r2 cmp r1, #CHIP_REV_2_0 - ldrhs r3, =CCM_MPLL_399_HZ - bhs 1f - ldr r2, [r0, #CLKCTL_PDR0] + movhs r2, #CLKMODE_CONSUMER + ldrlo r2, [r0, #CLKCTL_PDR0] tst r2, #CLKMODE_CONSUMER ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/ ldreq r3, =CCM_MPLL_399_HZ /* auto path*/ @@ -224,7 +223,7 @@ str r1, [r0, #CLKCTL_PDR0] ldr r1, [r0, #CLKCTL_CGR0] - orr r1, r1, #0x00300000 + orr r1, r1, #0x0C300000 str r1, [r0, #CLKCTL_CGR0] ldr r1, [r0, #CLKCTL_CGR1] @@ -322,14 +321,15 @@ lowlevel_init: init_drive_strength + init_clock + init_debug_board + cmp pc, #PHYS_SDRAM_1 - blo init_clock_start + blo init_sdram_start cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) blo skip_sdram_setup -init_clock_start: - init_clock - init_debug_board +init_sdram_start: /*init_sdram*/ setup_sdram skip_sdram_setup: |