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authorHaiying Wang <Haiying.Wang@freescale.com>2009-01-13 16:29:28 -0500
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2009-01-13 16:58:46 -0600
commitb5f65dfa9aa8e068e62aba4733dc4fd97b1d9bf6 (patch)
tree86bc278f77095fe7d3279605e972eb45007e976c /board/freescale/mpc8572ds/tlb.c
parent950264317eb9594b2b5ee2fb65206200a1c6007a (diff)
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Some changes of TLB entry setting for MPC8572DS
- Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode, all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0 can not access PIXIS_BASE anymore (any access will cause DataTLBError exception) - Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Diffstat (limited to 'board/freescale/mpc8572ds/tlb.c')
-rw-r--r--board/freescale/mpc8572ds/tlb.c7
1 files changed, 3 insertions, 4 deletions
diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c
index 8d1f646..829896a 100644
--- a/board/freescale/mpc8572ds/tlb.c
+++ b/board/freescale/mpc8572ds/tlb.c
@@ -41,10 +41,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
/* TLB 1 */
/* *I*** - Covers boot page */
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
@@ -86,6 +82,9 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_1M, 1),
+ SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 8, BOOKE_PAGESZ_4K, 1),
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);