summaryrefslogtreecommitdiff
path: root/board/freescale/mpc8572ds/tlb.c
diff options
context:
space:
mode:
authorKumar Gala <galak@kernel.crashing.org>2008-12-02 16:08:39 -0600
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2009-01-23 17:03:13 -0600
commit5af0fdd81c3370c3a51421208fda568bdcbbec23 (patch)
tree5fbd9f1b25951176fdaaa9d7eb76dd486930e6e5 /board/freescale/mpc8572ds/tlb.c
parenta6e04c344ad1eefd47a75484441b385da815b8df (diff)
downloadu-boot-imx-5af0fdd81c3370c3a51421208fda568bdcbbec23.zip
u-boot-imx-5af0fdd81c3370c3a51421208fda568bdcbbec23.tar.gz
u-boot-imx-5af0fdd81c3370c3a51421208fda568bdcbbec23.tar.bz2
85xx: Introduce CONFIG_SYS_PCI*_MEM_VIRT for FSL boards
Introduce a new define to seperate out the virtual address that PCI memory is at from the physical address. In most situations these are mapped 1:1. However any code accessing the bus should use VIRT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/freescale/mpc8572ds/tlb.c')
-rw-r--r--board/freescale/mpc8572ds/tlb.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c
index 6cb3eb1..594ff05 100644
--- a/board/freescale/mpc8572ds/tlb.c
+++ b/board/freescale/mpc8572ds/tlb.c
@@ -59,16 +59,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
0, 2, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_1G, 1),
/* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),