diff options
| author | Kumar Gala <galak@kernel.crashing.org> | 2010-12-17 06:53:52 -0600 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-01-14 01:32:20 -0600 |
| commit | 18ea5551307866af06eb7628ec05b1959212efa0 (patch) | |
| tree | 7871c2bce046a93958b5a3704f44cb8acc2ab889 /board/freescale/mpc8572ds/law.c | |
| parent | a4aafcc990c12816cfd4644e5c003d8556b6236b (diff) | |
| download | u-boot-imx-18ea5551307866af06eb7628ec05b1959212efa0.zip u-boot-imx-18ea5551307866af06eb7628ec05b1959212efa0.tar.gz u-boot-imx-18ea5551307866af06eb7628ec05b1959212efa0.tar.bz2 | |
powerpc/85xx: Rework MPC8572DS pci_init_board to use common FSL PCIe code
Remove duplicated code in MPC8572DS board and utilize the common
fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.
Signed-off-by: Chenhui Zhao <b26998@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/freescale/mpc8572ds/law.c')
| -rw-r--r-- | board/freescale/mpc8572ds/law.c | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/board/freescale/mpc8572ds/law.c b/board/freescale/mpc8572ds/law.c index e13bb53..7c63f84 100644 --- a/board/freescale/mpc8572ds/law.c +++ b/board/freescale/mpc8572ds/law.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008, 2010 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -29,12 +29,6 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2), - SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), - SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3), - SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), }; |