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| author | Masahiro Yamada <yamada.m@jp.panasonic.com> | 2015-02-27 02:27:06 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.m@jp.panasonic.com> | 2015-03-01 00:03:21 +0900 |
| commit | 105a9e705efaeeac63e795e2a184b0a18db0ac5a (patch) | |
| tree | 3143ea2278a368183cab2ac11880fd5427004352 /board/freescale/mpc8572ds/ddr.c | |
| parent | b76fa3a34ba8d64e75781c2d177a9a631d06d214 (diff) | |
| download | u-boot-imx-105a9e705efaeeac63e795e2a184b0a18db0ac5a.zip u-boot-imx-105a9e705efaeeac63e795e2a184b0a18db0ac5a.tar.gz u-boot-imx-105a9e705efaeeac63e795e2a184b0a18db0ac5a.tar.bz2 | |
ARM: UniPhier: remove SSC_WAY_SIZE and SSC_NUM_ENTRIES macros
Each way of the system cache has 256 entries for PH1-Pro4 and older
SoCs, whereas 512 entries for PH1-Pro5 and newer SoCs. The line
size is still 128 byte. Thus, the way size is 32KB/64KB for old/new
SoCs.
To keep lowlevel_init SoC-independent, set BOOT_RAM_SIZE to the
constant value 32KB. It is large enough for temporary RAM and
should work for all the SoCs of UniPhier family.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Diffstat (limited to 'board/freescale/mpc8572ds/ddr.c')
0 files changed, 0 insertions, 0 deletions