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authorKumar Gala <galak@kernel.crashing.org>2008-01-16 10:04:42 -0600
committerKumar Gala <galak@kernel.crashing.org>2008-01-16 23:21:56 -0600
commitc8c41d4a80b1a8ad5984a287d81ea780496259f8 (patch)
treed16801f7e70a98bc8f7f636bc458ccbc087bbe0c /board/freescale/mpc8568mds
parent54a5070115eff38e9b324b78abdfa0b4520580b9 (diff)
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85xx: Use proper defines for PCI addresses
We should be using the _MEM_PHYS for LAW and TLB setup and not _MEM_BASE. While _MEM_BASE & _MEM_PHYS are normally the same, _MEM_BASE should only be used for configuring the PCI ATMU. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/freescale/mpc8568mds')
-rw-r--r--board/freescale/mpc8568mds/init.S4
-rw-r--r--board/freescale/mpc8568mds/law.c4
2 files changed, 4 insertions, 4 deletions
diff --git a/board/freescale/mpc8568mds/init.S b/board/freescale/mpc8568mds/init.S
index 39819ab..c777eb1 100644
--- a/board/freescale/mpc8568mds/init.S
+++ b/board/freescale/mpc8568mds/init.S
@@ -140,8 +140,8 @@ tlb1_entry:
*/
.long FSL_BOOKE_MAS0(1, 2, 0)
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
- .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
- .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+ .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G))
+ .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
/*
* TLBe 3: 64M Non-cacheable, guarded
diff --git a/board/freescale/mpc8568mds/law.c b/board/freescale/mpc8568mds/law.c
index b35bbcd..5e96ea7 100644
--- a/board/freescale/mpc8568mds/law.c
+++ b/board/freescale/mpc8568mds/law.c
@@ -50,8 +50,8 @@
*/
struct law_entry law_table[] = {
- SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
- SET_LAW_ENTRY(3, CFG_PCIE1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+ SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+ SET_LAW_ENTRY(3, CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI),
SET_LAW_ENTRY(5, CFG_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
SET_LAW_ENTRY(6, CFG_SRIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),