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| author | Ed Swarthout <Ed.Swarthout@freescale.com> | 2007-07-27 01:50:51 -0500 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2007-08-14 01:38:40 -0500 |
| commit | 837f1ba05cfb248aba5ab8e1fb1bfeefa07d5962 (patch) | |
| tree | afb8a02fe74416106236caa33265e4958c453c5a /board/freescale/mpc8544ds/init.S | |
| parent | 61a21e980a7b9188424d04f1c265fdc5c21c7e85 (diff) | |
| download | u-boot-imx-837f1ba05cfb248aba5ab8e1fb1bfeefa07d5962.zip u-boot-imx-837f1ba05cfb248aba5ab8e1fb1bfeefa07d5962.tar.gz u-boot-imx-837f1ba05cfb248aba5ab8e1fb1bfeefa07d5962.tar.bz2 | |
8544ds PCIE support
PCI1 LAW mapping should use CFG_PCI1_MEM_PHY and not _BASE address.
Enable LBC and ECM errors and clear error registers.
Add tftpflash env var to get uboot from tftp server and flash it.
Add pci/pcie convenience env vars to display register space:
"run pcie3regs" to see all pcie3 ccsr registers
"run pcie3cfg" to see all cfg registers
Whitespace cleanup and MPC8544DS.h
Enable CONFIG_INTERRUPTS.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/freescale/mpc8544ds/init.S')
| -rw-r--r-- | board/freescale/mpc8544ds/init.S | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/board/freescale/mpc8544ds/init.S b/board/freescale/mpc8544ds/init.S index 296fee5..ea7d54d 100644 --- a/board/freescale/mpc8544ds/init.S +++ b/board/freescale/mpc8544ds/init.S @@ -52,8 +52,8 @@ */ #define entry_start \ - mflr r1 ; \ - bl 0f ; + mflr r1 ; \ + bl 0f ; #define entry_end \ 0: mflr r0 ; \ @@ -214,7 +214,7 @@ law_entry: .long 0 .long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN - .long (CFG_PCI1_MEM_BASE>>12) & 0xfffff + .long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M) .long (CFG_PCI1_IO_PHYS>>12) & 0xfffff |