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| author | Tom Rix <Tom.Rix@windriver.com> | 2010-01-18 08:08:32 -0600 |
|---|---|---|
| committer | Tom Rix <Tom.Rix@windriver.com> | 2010-01-18 08:08:32 -0600 |
| commit | a7709d926dbc7cb1541034fcf2b21ce3e838cb12 (patch) | |
| tree | 72c58261577bc00d98dbd208e4fa95dfbb2487a5 /board/freescale/mpc8536ds | |
| parent | 1c2a8e359ebbec0dbef62f5b54c72f9cd72ccd59 (diff) | |
| parent | 88ffb2665cd066b6b20cfaade13929d4e8428dde (diff) | |
| download | u-boot-imx-a7709d926dbc7cb1541034fcf2b21ce3e838cb12.zip u-boot-imx-a7709d926dbc7cb1541034fcf2b21ce3e838cb12.tar.gz u-boot-imx-a7709d926dbc7cb1541034fcf2b21ce3e838cb12.tar.bz2 | |
Merge branch 't-ml-master' into t-master
Diffstat (limited to 'board/freescale/mpc8536ds')
| -rw-r--r-- | board/freescale/mpc8536ds/mpc8536ds.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index f8292cf..81a56b5 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -226,7 +226,7 @@ void pci_init_board(void) SET_STD_PCIE_INFO(pci_info[num], 3); pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); printf (" PCIE3 connected to Slot3 as %s (base address %lx)\n", - pcie_ep ? "End Point" : "Root Complex", + pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie3_hose, first_free_busno); @@ -246,7 +246,7 @@ void pci_init_board(void) SET_STD_PCIE_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); printf (" PCIE1 connected to Slot1 as %s (base address %lx)\n", - pcie_ep ? "End Point" : "Root Complex", + pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie1_hose, first_free_busno); @@ -266,7 +266,7 @@ void pci_init_board(void) SET_STD_PCIE_INFO(pci_info[num], 2); pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); printf (" PCIE2 connected to Slot 2 as %s (base address %lx)\n", - pcie_ep ? "End Point" : "Root Complex", + pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie2_hose, first_free_busno); |