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authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2008-10-16 15:01:15 +0200
committerWolfgang Denk <wd@denx.de>2008-10-18 21:54:03 +0200
commit6d0f6bcf337c5261c08fabe12982178c2c489d76 (patch)
treeae13958ffa9c6b58c2ea97aac07a4ad2f04a350f /board/freescale/mpc8323erdb
parent71edc271816ec82cf0550dd6980be2da3cc2ad9e (diff)
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rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'board/freescale/mpc8323erdb')
-rw-r--r--board/freescale/mpc8323erdb/mpc8323erdb.c62
1 files changed, 31 insertions, 31 deletions
diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c
index f5220ab..8680a19 100644
--- a/board/freescale/mpc8323erdb/mpc8323erdb.c
+++ b/board/freescale/mpc8323erdb/mpc8323erdb.c
@@ -75,14 +75,14 @@ int fixed_sdram(void);
phys_size_t initdram(int board_type)
{
- volatile immap_t *im = (immap_t *) CFG_IMMR;
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize = 0;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
return -1;
/* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
msize = fixed_sdram();
@@ -95,12 +95,12 @@ phys_size_t initdram(int board_type)
************************************************************************/
int fixed_sdram(void)
{
- volatile immap_t *im = (immap_t *) CFG_IMMR;
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize = 0;
u32 ddr_size;
u32 ddr_size_log2;
- msize = CFG_DDR_SIZE;
+ msize = CONFIG_SYS_DDR_SIZE;
for (ddr_size = msize << 20, ddr_size_log2 = 0;
(ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
if (ddr_size & 1) {
@@ -109,18 +109,18 @@ int fixed_sdram(void)
}
im->sysconf.ddrlaw[0].ar =
LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
- im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
- im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
- im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
- im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
- im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
- im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
- im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
- im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
- im->ddr.sdram_mode = CFG_DDR_MODE;
- im->ddr.sdram_mode2 = CFG_DDR_MODE2;
- im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+ im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
+ im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+ im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+ im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+ im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+ im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+ im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+ im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+ im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+ im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
__asm__ __volatile__ ("sync");
udelay(200);
@@ -137,28 +137,28 @@ int checkboard(void)
static struct pci_region pci_regions[] = {
{
- bus_start: CFG_PCI1_MEM_BASE,
- phys_start: CFG_PCI1_MEM_PHYS,
- size: CFG_PCI1_MEM_SIZE,
+ bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+ size: CONFIG_SYS_PCI1_MEM_SIZE,
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
},
{
- bus_start: CFG_PCI1_MMIO_BASE,
- phys_start: CFG_PCI1_MMIO_PHYS,
- size: CFG_PCI1_MMIO_SIZE,
+ bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+ size: CONFIG_SYS_PCI1_MMIO_SIZE,
flags: PCI_REGION_MEM
},
{
- bus_start: CFG_PCI1_IO_BASE,
- phys_start: CFG_PCI1_IO_PHYS,
- size: CFG_PCI1_IO_SIZE,
+ bus_start: CONFIG_SYS_PCI1_IO_BASE,
+ phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+ size: CONFIG_SYS_PCI1_IO_SIZE,
flags: PCI_REGION_IO
}
};
void pci_init_board(void)
{
- volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
struct pci_region *reg[] = { pci_regions };
@@ -167,10 +167,10 @@ void pci_init_board(void)
clk->occr |= 0xe0000000;
/* Configure PCI Local Access Windows */
- pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
- pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
mpc83xx_pci_init(1, reg, 0);
@@ -186,7 +186,7 @@ void ft_board_setup(void *blob, bd_t *bd)
}
#endif
-#if defined(CFG_I2C_MAC_OFFSET)
+#if defined(CONFIG_SYS_I2C_MAC_OFFSET)
int mac_read_from_eeprom(void)
{
uchar buf[28];
@@ -196,9 +196,9 @@ int mac_read_from_eeprom(void)
unsigned char enetvar[32];
/* Read MAC addresses from EEPROM */
- if (eeprom_read(CFG_I2C_EEPROM_ADDR, CFG_I2C_MAC_OFFSET, buf, 28)) {
+ if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_MAC_OFFSET, buf, 28)) {
printf("\nEEPROM @ 0x%02x read FAILED!!!\n",
- CFG_I2C_EEPROM_ADDR);
+ CONFIG_SYS_I2C_EEPROM_ADDR);
} else {
if (crc32(crc, buf, 24) == *(unsigned int *)&buf[24]) {
printf("Reading MAC from EEPROM\n");