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authorTom Rini <trini@konsulko.com>2016-09-26 13:24:46 -0400
committerTom Rini <trini@konsulko.com>2016-09-26 17:10:56 -0400
commitcbe7706ab8aab06c18edaa9b120371f9c8012728 (patch)
treeebbfacedf031c33969d8d2e4d7459904b7fc1647 /board/freescale/ls1046aqds/ddr.h
parent8f2fe0c86c56175dd7d5d0e3bc26bef41f224f03 (diff)
parent295a24b3d6a751b79373e7ff2199d91765cae8a9 (diff)
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Merge git://git.denx.de/u-boot-fsl-qoriq
trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'board/freescale/ls1046aqds/ddr.h')
-rw-r--r--board/freescale/ls1046aqds/ddr.h44
1 files changed, 44 insertions, 0 deletions
diff --git a/board/freescale/ls1046aqds/ddr.h b/board/freescale/ls1046aqds/ddr.h
new file mode 100644
index 0000000..b594032
--- /dev/null
+++ b/board/freescale/ls1046aqds/ddr.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+
+void erratum_a008850_post(void);
+
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
+ */
+ {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
+ {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,},
+ {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
+ {2, 2300, 0, 8, 9, 0x0A0C0D11, 0x1214150E,},
+ {}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+
+#endif