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authorYork Sun <yorksun@freescale.com>2015-12-04 11:57:08 -0800
committerYork Sun <yorksun@freescale.com>2015-12-15 08:57:33 +0800
commitc107c0c05c988ac6cfba6de60c90f105bbea0e1e (patch)
tree5c3c98cf44b3e8991687875e985ce4d73485a3cf /board/freescale/ls1043aqds
parente81495224f732f17ae6f379baf23b90cd1d5cb5f (diff)
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armv8: fsl-layerscape: Make DDR non secure in MMU tables
DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/ls1043aqds')
-rw-r--r--board/freescale/ls1043aqds/ddr.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c
index 705e384..42d9068 100644
--- a/board/freescale/ls1043aqds/ddr.c
+++ b/board/freescale/ls1043aqds/ddr.c
@@ -126,6 +126,15 @@ phys_size_t initdram(int board_type)
void dram_init_banksize(void)
{
+ /*
+ * gd->secure_ram tracks the location of secure memory.
+ * It was set as if the memory starts from 0.
+ * The address needs to add the offset of its bank.
+ */
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+ gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
+ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
}