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| author | Xiubo Li <Li.Xiubo@freescale.com> | 2014-11-21 17:40:59 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-12-11 09:42:22 -0800 |
| commit | 660673af4fd10c544ceeedeb524ba92c27dbc586 (patch) | |
| tree | 2979c885f915d9aa5561a7977ac2c1b3543aa0ff /board/freescale/ls1021atwr/MAINTAINERS | |
| parent | e87f3b308c454f6e78b02da857936c7d012c385b (diff) | |
| download | u-boot-imx-660673af4fd10c544ceeedeb524ba92c27dbc586.zip u-boot-imx-660673af4fd10c544ceeedeb524ba92c27dbc586.tar.gz u-boot-imx-660673af4fd10c544ceeedeb524ba92c27dbc586.tar.bz2 | |
ARM: ls102xa: Setting device's stream id for SMMUs.
LS1 has 4 SMMUs for address translation of the masters. All the
SMMUs' stream IDs are 8-bit. The address translation depends on the
stream ID of the incoming transaction.
Each master has unique stream ID assigned to it and is configurable
through SCFG registers. The stream ID for the masters is identical
and share the same register field of STREAM ID registers.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/ls1021atwr/MAINTAINERS')
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