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authorBenoît Thébaudeau <benoit.thebaudeau@advansee.com>2013-01-30 11:19:14 +0000
committerStefano Babic <sbabic@denx.de>2013-02-12 13:52:30 +0100
commitaa53149e1108ab9395ee8309ce6f90480bfdf34b (patch)
tree2353fac130d22844bf03a50b7304899f48963d17 /board/freescale/imx/ddr
parent6904e377465db6c731adf4fb0eb67e55454606d7 (diff)
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imx: mx6q DDR3 init: Fix tXPR
MMDC1_MDOR.tXPR should be set as specified for the JEDEC DDR3 timing tXPR. For all DDR3 speed bins: tXPR(min) = max(5 nCK, tRFC(min) + 10 ns) tRFC(2 Gb) = 160 ns All the users of mx6q_4x_mt41j128.cfg have a 2-Gb density (Micron MT41J128M16HA-15E or SK hynix H5TQ2G63BFR-H9C for i.MX6Q SABRE Lite, and Micron MT41K128M16JT-125:K for i.MX6 SABRE SD). Hence, MMDC1_MDOR.tXPR should be set to max(5 nCK, 170 ns), which is 170 ns and 91 nCK at 532 MHz, encoded as 0x5A in the bit-field MMDC1_MDOR[23:16]. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Diffstat (limited to 'board/freescale/imx/ddr')
-rw-r--r--board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg2
1 files changed, 1 insertions, 1 deletions
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index 9ac8027..1c24da8 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -114,7 +114,7 @@ DATA 4 0x021b0010 0xFF538F64
DATA 4 0x021b0014 0x01FF00DB
DATA 4 0x021b002c 0x000026D2
-DATA 4 0x021b0030 0x005B0E21
+DATA 4 0x021b0030 0x005A0E21
DATA 4 0x021b0008 0x09444040
DATA 4 0x021b0004 0x00025576
DATA 4 0x021b0040 0x00000027