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| author | Kumar Gala <galak@kernel.crashing.org> | 2011-02-09 02:00:08 +0000 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-04-27 22:29:04 -0500 |
| commit | e02aea61cb17fc1e39368e4911491305d805e886 (patch) | |
| tree | 4bbff9a3f7309744dbcea8f2de9e4529127d34b7 /board/freescale/corenet_ds/tlb.c | |
| parent | df8af0b4a63b6375e7abbaffe1f93cc01c34529c (diff) | |
| download | u-boot-imx-e02aea61cb17fc1e39368e4911491305d805e886.zip u-boot-imx-e02aea61cb17fc1e39368e4911491305d805e886.tar.gz u-boot-imx-e02aea61cb17fc1e39368e4911491305d805e886.tar.bz2 | |
powerpc: Add P3041DS/P5020DS board support (uses corenet_ds code)
The P3041DS & P5020DS boards are almost identical (except for the
processor in them). Additionally they are based on the P4080DS board
design so we use the some board code for all 3 boards.
Some ngPIXIS (FPGA) registers where reserved on P4080DS and now have
meaning on P3041DS/P5020DS. We utilize some of these for SERDES clock
configuration.
Additionally, the P3041DS/P5020DS support NAND.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Shaohui Xie <b21989@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/freescale/corenet_ds/tlb.c')
| -rw-r--r-- | board/freescale/corenet_ds/tlb.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/board/freescale/corenet_ds/tlb.c b/board/freescale/corenet_ds/tlb.c index fe77e79..38736b4 100644 --- a/board/freescale/corenet_ds/tlb.c +++ b/board/freescale/corenet_ds/tlb.c @@ -117,6 +117,16 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 13, BOOKE_PAGESZ_4M, 1), #endif +#ifdef CONFIG_SYS_NAND_BASE + /* + * *I*G - NAND + * entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so we use entry 16 for nand. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 16, BOOKE_PAGESZ_1M, 1), +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); |