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authorPo Liu <po.liu@freescale.com>2013-05-16 09:27:28 +0800
committerYork Sun <yorksun@freescale.com>2013-08-14 10:58:34 -0700
commit2810312043e5e78b3b072c1e7fe379a213170850 (patch)
tree36fd2411d105f8df4072151e72ce331c30201202 /board/freescale/c29xpcie
parent61033367a0d3b5c37ae14586f71e24c6e679ca71 (diff)
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powerpc/c29xpcie: add readme document for c29xpcie
Signed-off-by: Po Liu <Po.Liu@freescale.com>
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+Overview
+=========
+C29XPCIE board is a series of Freescale PCIe add-in cards to perform
+as public key crypto accelerator or secure key management module.
+It includes C293PCIE board, C293PCIE board and C291PCIE board.
+The Freescale C29x family is a high performance crypto co-processor.
+It combines a single e500v2 core with necessary SEC engines.
+(maximum core frequency 1000/1200 MHz).
+
+The C29xPCIE board features are as follows:
+Memory subsystem:
+ - 512Mbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
+ - 64 Mbyte NOR flash single-chip memory
+ - 4 Gbyte NAND flash memory
+ - 1 Mbit AT24C1024 I2C EEPROM
+ - 16 Mbyte SPI memory
+
+Interfaces:
+ - 10/100/1000 BaseT Ethernet ports:
+ - eTSEC1, RGMII: one 10/100/1000 port
+ - eTSEC2, RGMII: one 10/100/1000 port
+ - DUART interface:
+ - DUART interface: supports two UARTs up to 115200 bps for
+ console display
+
+Board connectors:
+ - Mini-ITX power supply connector
+ - JTAG/COP for debugging
+
+Physical Memory Map on C29xPCIE
+===============================
+Address Start Address End Memory type
+0x0_0000_0000 - 0x0_1fff_ffff 512MB DDR
+0xc_0000_0000 - 0xc_8fff_ffff 256MB PCIE memory
+0xf_ec00_0000 - 0xf_efff_ffff 64MB NOR flash
+0xf_ffb0_0000 - 0xf_ffb7_ffff 512KB SRAM
+0xf_ffc0_0000 - 0xf_ffc0_ffff 64KB PCIE IO
+0xf_ffdf_0000 - 0xf_ffdf_0fff 4KB CPLD
+0xf_ffe0_0000 - 0xf_ffef_ffff 1MB CCSR
+
+Serial Port Configuration on C29xPCIE
+=====================================
+Configure the serial port of the attached computer with the following values:
+ -Data rate: 115200 bps
+ -Number of data bits: 8
+ -Parity: None
+ -Number of Stop bits: 1
+ -Flow Control: Hardware/None
+
+Settings of DIP-switch
+======================
+ SW5[1:4]= 1111 and SW5[6]=0 for boot from 16bit NOR flash
+ SW5[1:4]= 0110 and SW5[6]=0 for boot from SPI flash
+Note: 1 stands for 'off', 0 stands for 'on'
+
+Build and program u-boot to NOR flash
+==================================
+1. Build u-boot.bin image example:
+ export ARCH=powerpc
+ export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
+ make C293PCIE
+
+2. Program u-boot.bin into NOR flash
+ => tftp $loadaddr $uboot
+ => protect off eff80000 +$filesize
+ => erase eff80000 +$filesize
+ => cp.b $loadaddr eff80000 $filesize
+
+3. Check SW5[1:4]= 1111 and SW5[6]=0, then power on.
+
+Alternate NOR bank
+==================
+There are four banks in C29XPCIE board, example to change bank booting:
+1. Program u-boot.bin into alternate NOR bank
+ => tftp $loadaddr $uboot
+ => protect off e9f80000 +$filesize
+ => erase e9f80000 +$filesize
+ => cp.b $loadaddr e9f80000 $filesize
+
+2. Switch to alternate NOR bank
+ => cpld_cmd reset altbank [bank]
+ - [bank] bank value select 1-4
+ - bank 1 on the flash 0x0000000~0x0ffffff
+ - bank 2 on the flash 0x1000000~0x1ffffff
+ - bank 3 on the flash 0x2000000~0x2ffffff
+ - bank 4 on the flash 0x3000000~0x3ffffff
+ or set SW5[7]= ON/OFF and SW5[7]= ON/OFF, then power on again.
+
+Build and program u-boot to SPI flash
+==================================
+1. Build u-boot-spi.bin image
+ make C29xPCIE_SPIFLASH_config; make
+ Need the boot_format tool to generate u-boot-spi.bin from the u-boot.bin.
+
+2. Program u-boot-spi.bin into SPI flash
+ => tftp $loadaddr $uboot-spi
+ => sf erase 0 100000
+ => sf write $loadaddr 0 $filesize
+
+3. Check SW5[1:4]= 0110 and SW5[6]=0, then power on.