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| author | Po Liu <po.liu@freescale.com> | 2014-01-10 10:10:59 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-01-21 13:42:40 -0800 |
| commit | eb6b458cef28c86603d56a27b9ee699b13c60c14 (patch) | |
| tree | ae4973790cc7d439f19255db39a5156c91120b22 /board/freescale/c29xpcie/cpld.c | |
| parent | 6609916efb74724e53db368dd48bfb290d4d9f4c (diff) | |
| download | u-boot-imx-eb6b458cef28c86603d56a27b9ee699b13c60c14.zip u-boot-imx-eb6b458cef28c86603d56a27b9ee699b13c60c14.tar.gz u-boot-imx-eb6b458cef28c86603d56a27b9ee699b13c60c14.tar.bz2 | |
powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
Using the TPL/SPL method to booting from 8k page NAND flash.
- Add 256kB size SRAM tlb for second step booting;
- Add spl.c for TPL image boot;
- Add spl_minimal.c for minimal SPL image;
- Add C29XPCIE_NAND configure;
- Modify C29XPCIE.h for nand config and enviroment;
Signed-off-by: Po Liu <Po.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/c29xpcie/cpld.c')
| -rw-r--r-- | board/freescale/c29xpcie/cpld.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/board/freescale/c29xpcie/cpld.c b/board/freescale/c29xpcie/cpld.c index 5cbccff..37722da 100644 --- a/board/freescale/c29xpcie/cpld.c +++ b/board/freescale/c29xpcie/cpld.c @@ -89,6 +89,7 @@ static void cpld_dump_regs(void) } #endif +#ifndef CONFIG_SPL_BUILD int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int rc = 0; @@ -129,3 +130,4 @@ U_BOOT_CMD( "cpld_cmd dump - display the CPLD registers\n" #endif ); +#endif |