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| author | Priyanka Jain <Priyanka.Jain@freescale.com> | 2013-07-02 09:22:23 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-08-09 12:41:40 -0700 |
| commit | f9d379a7078f93433a98f3402a27f582a3868878 (patch) | |
| tree | a2a9cc38f905d7b78dd28bb5a4eb6fa54b136928 /board/freescale/bsc9132qds/tlb.c | |
| parent | 64501c669851e45dd47699349dae6b5798c075a3 (diff) | |
| download | u-boot-imx-f9d379a7078f93433a98f3402a27f582a3868878.zip u-boot-imx-f9d379a7078f93433a98f3402a27f582a3868878.tar.gz u-boot-imx-f9d379a7078f93433a98f3402a27f582a3868878.tar.bz2 | |
board/bsc9132qds: Configure DSP DDR controller
BSC9132 SoC has two separate DDR controllers for PowerPC side and DSP side
DDR. They are mapped to PowerPC and DSP CCSR space respectively.
BSC9132QDS has two on-board MC34716EP DDR3 memory one connected to PowerPC
and other to DSP side controller.
Configure DSP DDR controller similar to PowerPC side DDR controller as
memories are exactly similar.
Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/bsc9132qds/tlb.c')
0 files changed, 0 insertions, 0 deletions