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authorYork Sun <yorksun@freescale.com>2013-06-25 11:37:48 -0700
committerYork Sun <yorksun@freescale.com>2013-08-09 12:41:39 -0700
commitc63e137014cf148bc1d234128941dccee3d519ae (patch)
treeafb69c22c33459d14a174973083e2a70e5f49ea7 /board/freescale/bsc9132qds/ddr.c
parentb61e06156660579ea6e248abd2506ebdd85e7a14 (diff)
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powerpc/mpc8xxx: Add memory reset control
JEDEC spec requires the clocks to be stable before deasserting reset signal for RDIMMs. Clocks start when any chip select is enabled and clock control register is set. This patch also adds the interface to toggle memory reset signal if needed by the boards. Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/bsc9132qds/ddr.c')
-rw-r--r--board/freescale/bsc9132qds/ddr.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/board/freescale/bsc9132qds/ddr.c b/board/freescale/bsc9132qds/ddr.c
index 05bea8a..fdea193 100644
--- a/board/freescale/bsc9132qds/ddr.c
+++ b/board/freescale/bsc9132qds/ddr.c
@@ -109,7 +109,7 @@ phys_size_t fixed_sdram(void)
strmhz(buf, ddr_freq));
ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
- fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+ fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
LAW_TRGT_IF_DDR_1) < 0) {