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authorShaveta Leekha <shaveta@freescale.com>2013-03-25 07:40:24 +0000
committerAndy Fleming <afleming@freescale.com>2013-05-24 16:54:14 -0500
commit6eaeba23ddc5ccde5c97ef919ffcbf44ecad73dd (patch)
treeaa6aaeac0dc0fa083b3edae9420050318e652e9d /board/freescale/b4860qds
parente14cdc0a695d4cdb40843e1e7c6ee29c471a3fcc (diff)
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powerpc/b4860qds: Add LAW Target ID and Create LAW entry for Maple
Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/freescale/b4860qds')
-rw-r--r--board/freescale/b4860qds/law.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/board/freescale/b4860qds/law.c b/board/freescale/b4860qds/law.c
index abaad7a..b26725b 100644
--- a/board/freescale/b4860qds/law.c
+++ b/board/freescale/b4860qds/law.c
@@ -33,6 +33,9 @@ struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
#endif
SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_MAPLE_MEM_PHYS
+ SET_LAW(CONFIG_SYS_MAPLE_MEM_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_MAPLE),
+#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
/* Limit DCSR to 32M to access NPC Trace Buffer */
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),