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| author | York Sun <york.sun@nxp.com> | 2016-12-28 08:43:45 -0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-01-04 19:40:52 -0500 |
| commit | 51370d561842ae7438337e77a93177e13796ac45 (patch) | |
| tree | da97bb17019e198360bd99d81e9d98a533c014b4 /board/freescale/b4860qds | |
| parent | 66e399b68d20d96a90ba391d75c2290bd63bf4a5 (diff) | |
| download | u-boot-imx-51370d561842ae7438337e77a93177e13796ac45.zip u-boot-imx-51370d561842ae7438337e77a93177e13796ac45.tar.gz u-boot-imx-51370d561842ae7438337e77a93177e13796ac45.tar.bz2 | |
ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and CONFIG_SYS_NUM_DDR_CTRLS
These two macros are used for the same thing, the total number of DDR
controllers for a given SoC. Use SYS_NUM_DDR_CTRLS in Kconfig and
merge existing usage.
Signed-off-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'board/freescale/b4860qds')
| -rw-r--r-- | board/freescale/b4860qds/ddr.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c index 3885acc..99cd884 100644 --- a/board/freescale/b4860qds/ddr.c +++ b/board/freescale/b4860qds/ddr.c @@ -213,7 +213,7 @@ unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo, debug("rank density is 0x%llx, ctlr density is 0x%llx\n", rank_density, ctlr_density); - for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) { + for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) { switch (pinfo->memctl_opts[i].memctl_interleaving_mode) { case FSL_DDR_CACHE_LINE_INTERLEAVING: case FSL_DDR_PAGE_INTERLEAVING: @@ -237,7 +237,7 @@ unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo, * Simple linear assignment if memory * controllers are not interleaved. */ - for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) { + for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) { total_ctlr_mem = 0; pinfo->common_timing_params[i].base_address = current_mem_base; |