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authorStephen George <stephen.george@freescale.com>2013-03-25 07:40:12 +0000
committerAndy Fleming <afleming@freescale.com>2013-05-24 16:54:12 -0500
commit49e946cb6ae0448492147ffcb9dcd7d0af1eab4d (patch)
tree07118135410c7b399c8ac780b6fa803ceebdfaea /board/freescale/b4860qds/law.c
parent94025b1cd8d9959ebf987a7f6382d513c606ecf1 (diff)
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board/t4240qds, b4860qds: LAW/TLB for DCSR set to size 32M
Debug trace buffers are memory mapped in DCSR space beyond 4M. Signed-off-by: Stephen George <stephen.george@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/freescale/b4860qds/law.c')
-rw-r--r--board/freescale/b4860qds/law.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/board/freescale/b4860qds/law.c b/board/freescale/b4860qds/law.c
index 4142e01..abaad7a 100644
--- a/board/freescale/b4860qds/law.c
+++ b/board/freescale/b4860qds/law.c
@@ -34,7 +34,8 @@ struct law_entry law_table[] = {
#endif
SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+ /* Limit DCSR to 32M to access NPC Trace Buffer */
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
#endif
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),